參數(shù)資料
型號: ADC700SH
英文描述: 16-Bit Resolution With Microprocessor Interface A/D CONVERTER
中文描述: 16位分辨率,微處理器接口的A / D轉換器
文件頁數(shù): 12/12頁
文件大?。?/td> 148K
代理商: ADC700SH
12
ADC700
FIGURE 12. Using Sample/Hold with ADC700 Requires
Time Delay Between Sample and Start-of-Con-
version.
Sample
Hold
Start Conversion
1μs to 3μs
Mode
Control
ADC700
WR
SHC76
Mode
Control
Analog
In
ADC700
Because the last data-word is stored in the data latch, it is
possible to read it during the next A/D conversion. Assertion
of CS and HBEN for reading parallel data should be timed
from Status going low. The two-byte read operation must be
complete before the conversion in process is complete or the
Data Read is invalid.
Serial Data is available during continuous conversion with
word synchronization available from STATUS.
USING A SAMPLE/HOLD WITH ADC700
Figure 12 illustrates using ADC700 with the Burr-Brown
SHC76. The sample-to-hold settling time (to 14 bits,
±
0.003%FSR) of the SHC76 is 1
μ
s typ, 3
μ
s max. The time
from the Status going High to the first conversion decision
is about 900ns. Therefore a time delay between the Sample-
to-Hold command to the WR command to the ADC700 is
required.
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相關代理商/技術參數(shù)
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