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參數資料
| 型號： | ADCLK954BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 1/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:12 40LFCSP |
| 標準包裝： | 750 |
| 系列： | SIGe |
| 類型： | 扇出緩沖器（分配），多路復用器 |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 2:12 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | LVPECL |
| 頻率 - 最大： | 4.8GHz |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 帶卷 (TR) |
Two Selectable Inputs, 12 LVPECL Outputs,
SiGe Clock Fanout Buffer
ADCLK954
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2009–2010 Analog Devices, Inc. All rights reserved.
FEATURES
2 selectable differential inputs
4.8 GHz operating frequency
75 fs rms broadband random jitter
On-chip input terminations
3.3 V power supply
APPLICATIONS
Low jitter clock distribution
Clock and data signal restoration
Level translation
Wireless communications
Wired communications
Medical and industrial imaging
ATE and high performance instrumentation
GENERAL DESCRIPTION
The ADCLK954 is an ultrafast clock fanout buffer fabricated on
the Analog Devices, Inc., proprietary XFCB3 silicon germa-
nium (SiGe) bipolar process. This device is designed for high
speed applications requiring low jitter.
The ADCLK954 is an ultrafast clock fanout buffer fabricated on
the Analog Devices, Inc., proprietary XFCB3 silicon germa-
nium (SiGe) bipolar process. This device is designed for high
speed applications requiring low jitter.
The device has two selectable differential inputs via the IN_SEL
control pin. Both inputs are equipped with center tapped,
differential, 100 Ω on-chip termination resistors. The inputs
accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),
and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A
VREFx pin is available for biasing ac-coupled inputs.
The device has two selectable differential inputs via the IN_SEL
control pin. Both inputs are equipped with center tapped,
differential, 100 Ω on-chip termination resistors. The inputs
accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended),
and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A
VREFx pin is available for biasing ac-coupled inputs.
The ADCLK954 features 12 full-swing emitter coupled logic
(ECL) output drivers. For LVPECL (positive ECL) operation,
bias VCC to the positive supply and VEE to ground. For ECL
operation, bias VCC to ground and VEE to the negative supply.
The ADCLK954 features 12 full-swing emitter coupled logic
(ECL) output drivers. For LVPECL (positive ECL) operation,
bias VCC to the positive supply and VEE to ground. For ECL
operation, bias VCC to ground and VEE to the negative supply.
The output stages are designed to directly drive 800 mV each
side into 50 Ω terminated to VCC 2 V for a total differential
output swing of 1.6 V.
The output stages are designed to directly drive 800 mV each
side into 50 Ω terminated to VCC 2 V for a total differential
output swing of 1.6 V.
The ADCLK954 is available in a 40-lead LFCSP and specified
for operation over the standard industrial temperature range of
40°C to +85°C.
The ADCLK954 is available in a 40-lead LFCSP and specified
for operation over the standard industrial temperature range of
40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
VT0
VREF0
VREF1
IN_SEL
CLK0
VT1
CLK1
LVPECL
ADCLK954
REFERENCE
07
96
8-
0
01
Figure 1.
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