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參數(shù)資料
| 型號： | ADCMP551BRQ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMPARATOR PECL/LVPECL 16QSOP |
| 標準包裝： | 98 |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 1 |
| 輸出類型： | 補充型，差分，LVPECL，開路發(fā)射極，PECL |
| 電壓 - 電源，單路/雙路(±)： | 3.14 V ~ 5.25 V |
| 電壓 - 輸入偏移（最小值）： | 10mV @ 3.3V |
| 電流 - 輸入偏壓（最小值）： | 28µA @ 3.3V |
| 電流 - 輸出（標準）： | 55mA @ 3.3V |
| 電流 - 靜態(tài)（最大值）： | 17mA |
| CMRR, PSRR（標準）： | 76dB CMRR，75dB PSRR |
| 傳輸延遲（最大）： | 0.625ns |
| 磁滯： | ± 0.5mV |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 安裝類型： | 表面貼裝 |
| 包裝： | 管件 |
Data Sheet
ADCMP551/ADCMP552/ADCMP553
Rev. A | Page 11 of 16
APPLICATIONS INFORMATION
The comparators in the ADCMP55x series are very high speed
devices. Consequently, high speed design techniques must be
employed to achieve the best performance. The most critical
aspect of any ADCMP55x design is the use of a low impedance
ground plane. A ground plane, as part of a multilayer board, is
recommended for proper high speed performance. Using a
continuous conductive plane over the surface of the circuit
board can create this, allowing breaks in the plane only for
necessary signal paths. The ground plane provides a low
inductance ground, eliminating any potential differences at
different ground points throughout the circuit board caused by
ground bounce. A proper ground plane also minimizes the
effects of stray capacitance on the circuit board.
It is also important to provide bypass capacitors for the power
supply in a high speed application. A 1 F electrolytic bypass
capacitor should be placed within 0.5 inches of each power
supply pin to ground. These capacitors reduce any potential
voltage ripples from the power supply. In addition, a 10 nF ceramic
capacitor should be placed as close to the power supply pins as
possible on the ADCMP55x to ground. These capacitors act as a
charge reservoir for the device during high frequency switching.
The LATCH ENABLE input is active low (latched). If the latching
function is not used, the LATCH ENABLE input pins may be
left open. The internal pull-ups on the latch pins set the latch to
transparent mode. If the latch is to be used, valid PECL voltages
are required on the inputs for proper operation. The PECL
voltages should be referenced to VCCI.
Occasionally, one of the two comparator stages within the
ADCMP551/ADCMP552 is not used. The inputs of the unused
comparator should not be allowed to float. The high internal
gain may cause the output to oscillate (possibly affecting the
comparator that is being used) unless the output is forced into a
fixed state. This is easily accomplished by ensuring that the two
inputs are at least one diode drop apart, while also appropriately
connecting the LATCH ENABLE and LATCH ENABLE inputs
as described previously.
The best performance is achieved with the use of proper PECL
terminations. The open-emitter outputs of the ADCMP55x are
designed to be terminated through 50 resistors to VCCO 2.0 V
or any other equivalent PECL termination. If high speed PECL
signals must be routed more than a centimeter, microstrip or
stripline techniques may be required to ensure proper transition
times and prevent output ringing.
CLOCK TIMING RECOVERY
Comparators are often used in digital systems to recover clock
timing signals. High speed square waves transmitted over a dist-
ance, even tens of centimeters, can become distorted due to stray
capacitance and inductance. Poor layout or improper termination
can also cause reflections on the transmission line, further dis-
torting the signal waveform. A high speed comparator can be
used to recover the distorted waveform while maintaining a
minimum of delay.
OPTIMIZING HIGH SPEED PERFORMANCE
As with any high speed comparator amplifier, proper design and
layout techniques should be used to ensure optimal performance
from the ADCMP55x. The performance limits of high speed
circuitry can easily be a result of stray capacitance, improper
ground impedance, or other layout issues.
Minimizing resistance from source to the input is an important
consideration in maximizing the high speed operation of the
ADCMP55x. Source resistance in combination with equivalent
input capacitance can cause a lagged response at the input, thus
delaying the output. The input capacitance of the ADCMP55x,
in combination with stray capacitance from an input pin to ground,
could result in several picofarads of equivalent capacitance. A
combination of 3 k source resistance and 5 pF input capacitance
yields a time constant of 15 ns, which is significantly slower than
the 500 ps capability of the ADCMP55x. Source impedances
should be significantly less than 100 for best performance.
Sockets should be avoided due to stray capacitance and inductance.
If proper high speed techniques are used, the ADCMP55x should
be free from oscillation when the comparator input signal passes
through the switching threshold.
COMPARATOR PROPAGATION DELAY
DISPERSION
The ADCMP55x has been specifically designed to reduce
propagation delay dispersion over an input overdrive range of
20 mV to 1 V. Propagation delay overdrive dispersion is the
change in propagation delay that results from a change in the
degree of overdrive (how far the switching point is exceeded by
the input). The overall result is a higher degree of timing
accuracy since the ADCMP55x is far less sensitive to input
variations than most comparator designs.
Propagation delay dispersion is an important specification in
critical timing applications such as ATE, bench instruments, and
nuclear instrumentation. Overdrive dispersion is defined as the
variation in propagation delay as the input overdrive conditions
are changed (Figure 18). For the ADCMP55x, overdrive dispersion
is typically 125 ps as the overdrive is changed from 20 mV to
1 V. This specification applies for both positive and negative
overdrive since the ADCMP55x has equal delays for positive-
and negative-going inputs.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| ADCMP551BRQZ | 功能描述:IC COMPARATOR PECL/LVPECL 16QSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 標準包裝:1 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，開路集電極，TTL 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:7mV @ 5V 電流 - 輸入偏壓（最小值）:0.25µA @ 5V 電流 - 輸出（標準）:84mA @ 5V 電流 - 靜態(tài)（最大值）:120µA CMRR, PSRR（標準）:- 傳輸延遲（最大）:600ns 磁滯:- 工作溫度:-40°C ~ 85°C 封裝/外殼:SC-74A，SOT-753 安裝類型:表面貼裝 包裝:剪切帶 (CT) 產品目錄頁面:1268 (CN2011-ZH PDF) 其它名稱:*LMV331M5*LMV331M5/NOPBLMV331M5CT |
| ADCMP551BRQZ-REEL7 | 功能描述:IC COMPARATOR PECL/LVPECL 16QSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標準）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| ADCMP552 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Single Supply High Speed PECL Comparators |
| ADCMP552BRQ | 功能描述:IC COMPARATOR PECL/LVPECL 20QSOP RoHS:否 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標準）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| ADCMP552BRQZ | 功能描述:IC COMPARATOR PECL/LVPECL 20QSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 類型:帶電壓基準 元件數(shù):4 輸出類型:開路漏極 電壓 - 電源，單路/雙路(±):2.5 V ~ 11 V，±1.25 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:10mV @ 5V 電流 - 輸入偏壓（最小值）:- 電流 - 輸出（標準）:0.015mA @ 5V 電流 - 靜態(tài)（最大值）:8.5µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:- 磁滯:- 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 安裝類型:表面貼裝 包裝:管件 產品目錄頁面:1386 (CN2011-ZH PDF) |
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