參數資料
| 型號： | ADCMP561BRQ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 13/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMP PECL DUAL HS 16-QSOP |
| 產品變化通告： | Product Discontinuation 05/Apr/2012 |
| 標準包裝： | 98 |
| 類型： | 帶鎖銷 |
| 元件數： | 2 |
| 輸出類型： | 補充型，差分，開路發(fā)射極，PECL |
| 電壓 - 電源，單路/雙路(±)： | ±4.75 V ~ 5.25 V |
| 電壓 - 輸入偏移（最小值）： | 2mV @ -5.2V，5V |
| 電流 - 輸入偏壓（最小值）： | 3µA @ -5.2V，5V |
| 電流 - 輸出（標準）： | 30mA |
| 電流 - 靜態(tài)（最大值）： | 5mA，28mA，13mA |
| CMRR, PSRR（標準）： | 80dB CMRR，85dB PSRR |
| 傳輸延遲（最大）： | 0.83ns |
| 磁滯： | ±1mV |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 安裝類型： | 表面貼裝 |
| 包裝： | 管件 |
| 配用： | EVAL-ADCMP561BRQZ-ND - BOARD EVALUATION ADCMP561BRQZ |
ADCMP561/ADCMP562
Rev. A | Page 6 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
04687-0-002
ADCMP561
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
–INA
+INA
QA
VDD
VEE
LEA
–INB
+INB
QB
GND
VCC
LEB
04687-0-003
ADCMP562
TOP VIEW
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
–INA
QA
VDD
VEE
LEA
VDD
+INA
HYSA
–INB
QB
GND
VCC
LEB
VDD
+INB
HYSB
Figure 4. ADCMP561 16-Lead QSOP Pin Configuration
Figure 5. ADCMP562 20-Lead QSOP Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
ADCMP561
ADCMP562
Mnemonic
Function
1
VDD
Logic Supply Terminal.
1
2
QA
One of two complementary outputs for Channel A. QA is logic high if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the
comparator is in compare mode). See the description of Pin LEA for more information.
2
3
QA
One of two complementary outputs for Channel A. QA is logic low if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the
comparator is in compare mode). See the description of Pin LEA for more information.
3
4
VDD
Logic Supply Terminal.
4
5
LEA
One of two complementary inputs for Channel A Latch Enable. In compare mode (logic high),
the output tracks changes at the input of the comparator. In the latch mode (logic low), the
output reflects the input state just prior to the comparator’s being placed in the latch mode.
LEA must be driven in conjunction with LEA. If left unconnected, the comparator defaults to
compare mode.
5
6
LEA
One of two complementary inputs for Channel A Latch Enable. In compare mode (logic low),
the output tracks changes at the input of the comparator. In latch mode (logic high), the
output reflects the input state just prior to the comparator’s being placed in the latch mode.
LEA must be driven in conjunction with LEA. If left unconnected, the comparator defaults to
compare mode.
6
7
VEE
Negative Supply Terminal.
7
8
INA
Inverting Analog Input of the Differential Input Stage for Channel A. The inverting A input must
be driven in conjunction with the noninverting A input.
8
9
+INA
Noninverting Analog Input of the Differential Input Stage for Channel A. The noninverting
A input must be driven in conjunction with the inverting A input.
10
HYSA
Programmable Hysteresis Input.
11
HYSB
Programmable Hysteresis Input.
9
12
+INB
Noninverting Analog Input of the Differential Input Stage for Channel B. The noninverting
B input must be driven in conjunction with the inverting B input.
10
13
INB
Inverting Analog Input of the Differential Input Stage for Channel B. The inverting B input must
be driven in conjunction with the noninverting B input.
11
14
VCC
Positive Supply Terminal.
12
15
LEB
One of two complementary inputs for Channel B Latch Enable. In compare mode (logic low),
the output tracks changes at the input of the comparator. In latch mode (logic high), the
output reflects the input state just prior to placing the comparator in the latch mode. LEB
must be driven in conjunction with LEB. If left unconnected, the comparator defaults to
compare mode.
13
16
LEB
One of two complementary inputs for Channel B Latch Enable. In compare mode (logic high),
the output tracks changes at the input of the comparator. In latch mode (logic low), the output
reflects the input state just prior to placing the comparator in the latch mode. LEB must be
driven in conjunction with LEB. If left unconnected, the comparator defaults to compare mode.
相關PDF資料 |
PDF描述 |
|---|---|
| ADCMP563BRQ | IC COMPARATOR ECL DUAL 16QSOP |
| ADCMP565BP | IC COMP DUAL ULTRA-FAST 20-PLCC |
| ADCMP566BCPZ | IC COMP DUAL ULTRA-FAST 32LFCSP |
| ADCMP567BCPZ | IC COMP DUAL ULTRA-FAST 32LFCSP |
| ADCMP573BCPZ-WP | IC COMPARATOR PECL 3.3-5 16LFCSP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADCMP561BRQZ | 功能描述:IC COMPARATOR PECL DUAL 16QSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 類型:帶電壓基準 元件數:4 輸出類型:開路漏極 電壓 - 電源，單路/雙路(±):2.5 V ~ 11 V，±1.25 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:10mV @ 5V 電流 - 輸入偏壓（最小值）:- 電流 - 輸出（標準）:0.015mA @ 5V 電流 - 靜態(tài)（最大值）:8.5µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:- 磁滯:- 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 安裝類型:表面貼裝 包裝:管件 產品目錄頁面:1386 (CN2011-ZH PDF) |
| ADCMP562 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual High Speed PECL Comparators |
| ADCMP562BRQ | 功能描述:IC COMPARATOR PECL DUAL 20QSOP RoHS:否 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數:1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標準）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
| ADCMP562BRQZ | 功能描述:IC COMPARATOR PECL DUAL 20-QSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 標準包裝:1 系列:- 類型:通用 元件數:1 輸出類型:CMOS，開路集電極，TTL 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:7mV @ 5V 電流 - 輸入偏壓（最小值）:0.25µA @ 5V 電流 - 輸出（標準）:84mA @ 5V 電流 - 靜態(tài)（最大值）:120µA CMRR, PSRR（標準）:- 傳輸延遲（最大）:600ns 磁滯:- 工作溫度:-40°C ~ 85°C 封裝/外殼:SC-74A，SOT-753 安裝類型:表面貼裝 包裝:剪切帶 (CT) 產品目錄頁面:1268 (CN2011-ZH PDF) 其它名稱:*LMV331M5*LMV331M5/NOPBLMV331M5CT |
| ADCMP562BRQZ-RL7 | 功能描述:IC COMPARATOR PECL DUAL 20QSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 類型:通用 元件數:1 輸出類型:CMOS，推挽式，滿擺幅，TTL 電壓 - 電源，單路/雙路(±):2.5 V ~ 5.5 V，±1.25 V ~ 2.75 V 電壓 - 輸入偏移（最小值）:5mV @ 5.5V 電流 - 輸入偏壓（最小值）:1pA @ 5.5V 電流 - 輸出（標準）:- 電流 - 靜態(tài)（最大值）:24µA CMRR, PSRR（標準）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:450ns 磁滯:±3mV 工作溫度:-40°C ~ 85°C 封裝/外殼:6-WFBGA，CSPBGA 安裝類型:表面貼裝 包裝:管件 其它名稱:Q3554586 |
發(fā)布緊急采購，3分鐘左右您將得到回復。