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參數(shù)資料
| 型號(hào)： | ADCMP572BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 0K |
| 描述： | IC COMPARATOR CML 3.3-5V 16LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 1 |
| 輸出類型： | CML，補(bǔ)充型 |
| 電壓 - 電源，單路/雙路(±)： | 3.1 V ~ 5.4 V |
| 電壓 - 輸入偏移（最小值）： | 2mV @ 3.3V |
| 電流 - 輸入偏壓（最小值）： | 25µA @ 3.3V |
| 電流 - 輸出（標(biāo)準(zhǔn)）： | 20mA |
| 電流 - 靜態(tài)（最大值）： | 52mA |
| CMRR, PSRR（標(biāo)準(zhǔn)）： | 65dB CMRR，74dB PSRR |
| 傳輸延遲（最大）： | 0.165ns |
| 磁滯： | ±1mV |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，CSP |
| 安裝類型： | 表面貼裝 |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADCMP572BCPZ-ND - BOARD EVALUATION ADCMP572BCP |
ADCMP572/ADCMP573
Rev. A | Page 13 of 16
TIMING INFORMATION
Figure 29 illustrates the ADCMP572/ADCMP573 compare and latch timing relationships. Table 4 provides definitions of the terms
shown in the figure.
50%
VN ± VOS
50%
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
LATCH ENABLE
tH
tPDL
tPDH
tPLOH
tPLOL
tR
tF
VIN
VOD
tS
tPL
04409-003
Figure 29. System Timing Diagram
Table 4. Timing Descriptions
Symbol
Timing
Description
tPDH
Input to output high delay
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.
tPDL
Input to output low delay
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.
tPLOH
Latch enable to output high delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
tPLOL
Latch enable to output low delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
tH
Minimum hold time
Minimum time after the negative transition of the latch enable signal that the input
signal must remain unchanged to be acquired and held at the outputs.
tPL
Minimum latch enable pulse width
Minimum time that the latch enable signal must be high to acquire an input signal
change.
tS
Minimum setup time
Minimum time before the negative transition of the latch enable signal that an input
signal change must be present to be acquired and held at the outputs.
tR
Output rise time
Amount of time required to transition from a low to a high output as measured at the
20% and 80% points.
tF
Output fall time
Amount of time required to transition from a high to a low output as measured at the
20% and 80% points.
VOD
Voltage overdrive
Difference between the input voltages VA and VB.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADCMP572BCPZ-WP | 功能描述:IC COMPARATOR CML 3.3-5V 16LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 類型:帶電壓基準(zhǔn) 元件數(shù):4 輸出類型:開路漏極 電壓 - 電源，單路/雙路(±):2.5 V ~ 11 V，±1.25 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:10mV @ 5V 電流 - 輸入偏壓（最小值）:- 電流 - 輸出（標(biāo)準(zhǔn)）:0.015mA @ 5V 電流 - 靜態(tài)（最大值）:8.5µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:- 磁滯:- 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 安裝類型:表面貼裝 包裝:管件 產(chǎn)品目錄頁面:1386 (CN2011-ZH PDF) |
| ADCMP572XCP | 制造商:Analog Devices 功能描述:CML ULTRAFAST 3.3V SINGLE SUPPLY COMPARATOR - Bulk |
| ADCMP573 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultrafast 3.3 V Single-Supply Comparators |
| ADCMP573BCP | 制造商:Analog Devices 功能描述:COMPARATOR SGL 5.4V 16LFCSP EP - Bulk |
| ADCMP573BCP-R2 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
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