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參數(shù)資料
| 型號： | ADCMP573BCPZ-WP |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMPARATOR PECL 3.3-5 16LFCSP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 1 |
| 輸出類型： | 補(bǔ)充型，PECL |
| 電壓 - 電源，單路/雙路(±)： | 3.1 V ~ 5.4 V |
| 電壓 - 輸入偏移（最小值）： | 2mV @ 3.3V |
| 電流 - 輸入偏壓（最小值）： | 25µA @ 3.3V |
| 電流 - 輸出（標(biāo)準(zhǔn)）： | 35mA |
| 電流 - 靜態(tài)（最大值）： | 80mA |
| CMRR, PSRR（標(biāo)準(zhǔn)）： | 65dB CMRR，74dB PSRR |
| 傳輸延遲（最大）： | 0.165ns |
| 磁滯： | ±1mV |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，CSP |
| 安裝類型： | 表面貼裝 |
| 包裝： | 托盤 - 晶粒 |
| 配用： | EVAL-ADCMP573BCPZ-ND - BOARD EVALUATION ADCMP573BCP |
ADCMP572/ADCMP573
Rev. A | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04409-026
5
V
CCI
6
LE
7
LE
8
V
CCO
/V
TT
ADCMP572
ADCMP573
TOP VIEW
(Not to Scale)
1
VTP
PIN1
2
VP
3
VN
4
VTN
16
V
CCI
15
GND
14
HY
S
13
GND
VCCO
12
Q
11
Q
10
VCCO
9
Figure 2. ADCMP572/ADCMP573 Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VTP
Termination Resistor Return Pin for VP Input.
2
VP
Noninverting Analog Input.
3
VN
Inverting Analog Input.
4
VTN
Termination Resistor Return Pin for VN Input.
5, 16
VCCI
Positive Supply Voltage for Input Stage.
6
LE
Latch Enable Input Pin, Inverting Side.
In compare mode (LE = low), the output tracks changes at the input of the comparator.
In latch mode (LE = high), the output reflects the input state just prior to the comparator’s being placed
into latch mode. LE must be driven in complement with LE.
7
LE
Latch Enable Input Pin, Noninverting Side.
In compare mode (LE = high), the output tracks changes at the input of the comparator.
In latch mode (LE = low), the output reflects the input state just prior to the comparator’s being placed
into latch mode. LE must be driven in complement with LE.
8
VCCO/VTT
Termination Return Pin for the LE/LE Input Pins.
For the ADCMP572 (CML output stage), this pin is internally connected to and also should be externally
connected to the positive VCCO supply.
For the ADCMP573 (RSPECL output stage), this pin should normally be connected to the VCCO – 2 V
termination potential.
9, 12
VCCO
Positive Supply Voltage for the CML/RSPECL Output Stage.
13, 15
GND
Ground.
10
Q
Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the
analog voltage at the inverting input, VN, provided the comparator is in compare mode. See the LE/LE
descriptions (Pins 6 and 7) for more information.
11
Q
Noninverting Output. Q is at logic high if the analog voltage at the noninverting input VP is greater
than the analog voltage at the inverting input, VN, provided the comparator is in compare mode.
See the LE/LE descriptions (Pins 6 and 7) for more information.
14
HYS
Hysteresis Control Pin. Leave this pin disconnected for zero hysteresis. Connect to GND with a suitably
sized resistor to add the desired amount of hysteresis. Refer to Figure 7 for proper sizing of RHYS
hysteresis control resistor.
Isolated
Heat Sink
N/C
The metallic back surface of the package is not electrically connected to any part of the circuit, and it
can be left floating for best electrical isolation between the package handle and the substrate of the
die. However, it can be soldered to the application board if improved thermal and/or mechanical
stability is desired. Exposed metal at package corners is connected to the heat sink paddle.
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