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參數(shù)資料
| 型號： | ADCMP600BKSZ-R2 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/16頁 |
| 文件大小： | 0K |
| 描述： | IC COMP TTL/CMOS 1CHAN SC70-5 |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 類型： | 通用 |
| 元件數(shù)： | 1 |
| 輸出類型： | CMOS，TTL |
| 電壓 - 電源，單路/雙路(±)： | 2.5 V ~ 5.5 V |
| 電壓 - 輸入偏移（最小值）： | 5mV @ 2.5V |
| 電流 - 輸入偏壓（最小值）： | 5µA @ 2.5V |
| 電流 - 輸出（標(biāo)準(zhǔn)）： | 50mA |
| 電流 - 靜態(tài)（最大值）： | 4mA |
| CMRR, PSRR（標(biāo)準(zhǔn)）： | 50dB CMRR，50dB PSRR |
| 傳輸延遲（最大）： | 5ns |
| 磁滯： | 2mV |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 6-TSSOP（5 引線），SC-88A，SOT-353 |
| 安裝類型： | 表面貼裝 |
| 包裝： | 帶卷 (TR) |
ADCMP600/ADCMP601/ADCMP602
Rev. A | Page 12 of 16
Leaving the LE/HYS pin disconnected results in a fixed
hysteresis of 2 mV; driving this pin high removes hysteresis. The
maximum hysteresis that can be applied using this pin is
approximately 160 mV. Figure 21 illustrates the amount of
hysteresis applied as a function of the external resistor value,
and Figure 11 illustrates hysteresis as a function of the current.
The hysteresis control pin appears as a 1.25 V bias voltage seen
through a series resistance of 7 k. The bias voltage changes
± 20% throughout the hysteresis control range. The advantages
of applying hysteresis in this manner are improved accuracy,
improved stability, reduced component count, and maximum
versatility. An external bypass capacitor is not recommended on
the HYS pin because it impairs the latch function and often
degrades the jitter performance of the device. As described in the
Using/Disabling the Latch Feature section, hysteresis control
need not compromise the latch function.
CROSSOVER BIAS POINT
In both op amps and comparators, rail-to-rail inputs of this type
have a dual front-end design. Certain devices are active near the
VCC rail and others are active near the GND rail. At some predeter-
mined point in the common-mode range, a crossover occurs. At
this point, normally VCC/2, the direction of the bias current reverses
and the measured offset voltages and currents change.
The ADCMP600/ADCMP601/ADCMP602 comparators
slightly elaborate on this scheme. Crossover points can be found
at approximately 0.8 V and 1.6 V.
0
50
150
250
450
350
550
650
50
100
150
200
250
05914-
030
H
YST
ER
ESI
S
(m
V)
HYSTERESIS RESISTOR (k
)
VCC = 5.5V
VCC = 2.5V
Figure 21. Hysteresis vs. RHYS Control Resistor
MINIMUM INPUT SLEW RATE REQUIREMENT
With the rated load capacitance and normal good PC Board
design practice, as discussed in the Optimizing Performance
section, these comparators should be stable at any input slew
rate with no hysteresis. Broadband noise from the input stage is
observed in place of the violent chattering seen with most other
high speed comparators. With additional capacitive loading or
poor bypassing, oscillation is observed. This oscillation is due to
the high gain bandwidth of the comparator in combination with
feedback parasitics in the package and PC board. In many
applications, chattering is not harmful.
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| ADCMP600BKSZ-REEL7 | 功能描述:IC COMP TTL/CMOS 1CHAN SC70-5 RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 類型:帶電壓基準(zhǔn) 元件數(shù):4 輸出類型:開路漏極 電壓 - 電源，單路/雙路(±):2.5 V ~ 11 V，±1.25 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:10mV @ 5V 電流 - 輸入偏壓（最小值）:- 電流 - 輸出（標(biāo)準(zhǔn)）:0.015mA @ 5V 電流 - 靜態(tài)（最大值）:8.5µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:- 磁滯:- 工作溫度:0°C ~ 70°C 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 安裝類型:表面貼裝 包裝:管件 產(chǎn)品目錄頁面:1386 (CN2011-ZH PDF) |
| ADCMP600BKSZ-RL | 功能描述:IC COMP TTL/CMOS 1CHAN SC70-5 RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 標(biāo)準(zhǔn)包裝:25 系列:- 類型:帶電壓基準(zhǔn) 元件數(shù):4 輸出類型:CMOS，開路漏極，TTL 電壓 - 電源，單路/雙路(±):2 V ~ 11 V，±1 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:10mV @ 5V 電流 - 輸入偏壓（最小值）:- 電流 - 輸出（標(biāo)準(zhǔn)）:0.015mA @ 5V 電流 - 靜態(tài)（最大值）:8.5µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:12µs 磁滯:50mV 工作溫度:0°C ~ 70°C 封裝/外殼:16-DIP（0.300"，7.62mm） 安裝類型:通孔 包裝:管件 |
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