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參數(shù)資料
| 型號： | ADCS-1021 |
| 英文描述： | ECONOLINE: REC3-S_DRW(Z)/H* - 3W DIP Package- 1kVDC Isolation- Wide Input 2:1 & 4:1- Regulated Output- 100% Burned In- UL94V-0 Package Material- Continuous Short Circiut Protection- Efficiency to 80% |
| 中文描述： | CMOS圖像傳感器 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 104K |
| 代理商： | ADCS-1021 |
2
Brief Introduction
The Agilent ADCS-2021 and
Agilent ADCS-1021 image sen-
sors act as normal CMOS digital
devices from the outside. Inter-
nal circuits are a combination of
sensitive analog and timing
circuits. Therefore, the designer
must pay attention to the PC
board layout and power supply
design. Writing to registers via an
I
2
C compatible two-wire interface
provides control of the sensor.
Sensor data is normally output
via an 8 or 10 bit parallel inter-
face (serial data output is also
available). Once the registers are
programmed the sensor is self-
clocking and all timing is inter-
nally generated. On chip pro-
grammable amplifiers provide a
way to separately adjust the red
green and blue pixels for a good
white balance. Analog to digital
conversion is also on chip and 8
or 10 bit digital data is output. A
data ready pulse follows each
valid pixel output. An end of row
signal follows each row and an
end of frame signal follows each
frame.
PCB Layout
Analog Vdd and analog ground
need to be routed separately
from digital V
dd
and digital
ground. Noisy circuits or ICs
should not be placed on the
opposite side of the PC board.
Heat producing circuits such as
microprocessors or LCD displays
should not be placed next to or
opposite from the sensor to
reduce noise in the image.
Power Supply
The sensor operates at 3.3 VDC.
There are two power supplies for
the sensor. Analog V
dd
and
Digital V
dd
. The two supplies and
grounds must be kept separate.
Two separate regulators provide
the best isolation. Any noise on
the analog supply will result in
noise in the image. Analog and
digital ground should be tied
together at a single point of
lowest impedance and noise.
Master Clock
The part requires a 50% duty cycle
master clock. Maximum clock
rates are 25 MHz for ADCS-2021
and 32 MHZ for ADCS-1021.
Reset
A hard reset is required before
the sensor will function properly.
Once the master clock is running,
assert nRST_nSTBY for 40 clock
cycles.
Register Communication
Communication (read/write) to
the sensor registers is via a two
wire serial interface
—
either a
synchronous I
2
C compatible or
half duplex UART (9600 baud
default). nTristate (pin 3
ADCS-1021 only) must be pulled
high for normal operation. The
ADCS-2021 does not have
nTristate.
Parallel Data Output
8 or 10 bit parallel data is output
from the sensor. A data ready
line (DRDY) is asserted when the
data is valid. The sensor acts as a
master in the way it outputs
data. There is no flow control or
data received handshake. Once
the RUN bit (CONTROL register)
is set, the image processor must
be ready to accept data at the
sensor rate and when the data is
presented.
Serial Data Output
In this mode, output data lines
D0 and D1 (the lower two bits of
the parallel data port) act as a
two wire serial interface.
Handshaking
At the end of one row of data, the
nROW line is asserted. At the end
of one frame of data, the
nFRAME_nSYNC line is asserted.
Registers
On the next page is a table of
sample register settings (see
Figure 1). These values are a
good starting point.
相關PDF資料 |
PDF描述 |
|---|---|
| ADCS-2021 | CMOS Image Sensors |
| ADCS-1121 | Monochrome CMOS Image Sensor (CIF) |
| ADCS-2121 | Monochrome CMOS Image Sensor (VGA) |
| ADC | |
| ADDC02812QMLH | Analog IC |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADCS-1120 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Agilent CMOS Monochrome Image Sensors |
| ADCS-1121 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Monochrome CMOS Image Sensor (CIF) |
| ADCS-2021 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:CMOS Image Sensors |
| ADCS-2120 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Agilent CMOS Monochrome Image Sensors |
| ADCS-2121 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Monochrome CMOS Image Sensor (VGA) |
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