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參數(shù)資料
型號: ADDAC80N-CBI-V
廠商: Analog Devices Inc
文件頁數(shù): 16/16頁
文件大?。?/td> 0K
描述: IC DAC 12-BIT BINARY MONO 24-DIP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準包裝: 15
設(shè)置時間: 2µs
位數(shù): 12
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 雙 ±
功率耗散(最大): 300mW
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: 24-DIP(0.600",15.24mm)
供應(yīng)商設(shè)備封裝: 24-PDIP
包裝: 管件
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): *
REV. B
ADDAC80/ADDAC85/ADDAC87
–9–
15V
+
IREF
DAC
IDAC
V–
+
OA
RGAIN
RBP
6.3k
6.3V
Figure 4. Bipolar Configuration
There are three types of drift errors over temperature: offset,
gain, and linearity. Offset drift causes a vertical translation of
the entire transfer curve; gain drift is a change in the slope of the
curve; and linearity drift represents a change in the shape of the
curve. The combination of these three drifts results in the com-
plete specification for total error over temperature.
Total error is defined as the deviation from a true straight line
transfer characteristic from exactly zero at a digital input that
calls for zero output to a point that is defined as full-scale. A
specification for total error over temperature assumes that both
the zero and full-scale points have been trimmed for zero error
at 25
°C. Total error is normally expressed as a percentage of the
full-scale range. In the bipolar situation, this means the total
range from –VFS to +VFS.
Several new design concepts not previously used in DAC80-type
devices contribute to a reduction in all the error factors over
temperature. The incorporation of low temperature coefficient
silicon-chromium thin-film resistors deposited on a single chip,
a patented, fully differential, emitter weighted, precision current
steering cell structure, and a T.C. trimmed buried Zener diode
reference element results in superior wide temperature range
performance. The gain setting resistors and bipolar offset resis-
tor are also fabricated on the chip with the same SiCr material
as the ladder network, resulting in low gain and offset drift.
MONOTONICITY AND LINEARITY
The initial linearity error of
±1/2 LSB max and the differential
linearity error of
±3/4 LSB max guarantee monotonic performance
over the specified range. It can therefore be assumed that linearity
errors are insignificant in computation of total temperature errors.
UNIPOLAR ERRORS
Temperature error analysis in the unipolar mode is straightforward:
there is an offset drift and a gain drift. The offset drift (which
comes from leakage currents and drift in the output amplifier
(OA)) causes a linear shift in the transfer curve as shown in
Figure 5. The gain drift causes a change in the slope of the
curve and results from reference drift, DAC drift, and drift in
RGAIN relative to the DAC resistors.
BIPOLAR RANGE ERRORS
The analysis is slightly more complex in the bipolar mode. In
this mode RBP is connected to the summing node of the output
amplifier (see Figure 4) to generate a current that exactly balances
the current of the MSB so that the output voltage is zero with
only the MSB on.
Note that if the DAC and application resistors track perfectly,
the bipolar offset drift will be zero even if the reference drifts. A
change in the reference voltage, which causes a shift in the bipolar
offset, will also cause an equivalent change in IREF and thus IDAC,
so that IDAC will always be exactly balanced by IBP with the MSB
turned on. This effect is shown in Figure 5. The net effect of the
reference drift then is simply to cause a rotation in the transfer
around bipolar zero. However, consideration of second order
effects (which are often overlooked) reveals the errors in the
bipolar mode. The unipolar offset drifts previously discussed
will have the same effect on the bipolar offset. A mismatch of RBP
to the DAC resistors is usually the largest component of bipolar
drift, but in the ADDAC80 this error is held to 10 ppm/
°C max.
Gain drift in the DAC also contributes to bipolar offset drift,
as well as full-scale drift, but again is held to 10 ppm/
°C max.
ACTUAL
GAIN SHIFT
IDEAL
OFFSET (ZERO) SHIFT
OUTPUT
UNIPOLAR
INPUT
OUTPUT
OFFSET SHIFT
BIPOLAR (IDEAL CASE)
GAIN SHIFT
INPUT
Figure 5. Unipolar and Bipolar Drifts
USING THE ADDAC80 SERIES
POWER SUPPLY CONNECTIONS
For optimum performance power supply decoupling capacitors
should be added as shown in the connection diagrams. These
capacitors (1
F electrolytic recommended) should be located
close to the ADDAC80. Electrolytic capacitors, if used, should
be paralleled with 0.01
F ceramic capacitors for optimum high
frequency performance.
EXTERNAL OFFSET AND GAIN ADJUSTMENT
Offset and gain may be trimmed by installing external OFFSET
and GAIN potentiometers. These potentiometers should be
connected as shown in the block diagrams and adjusted as
described below. TCR of the potentiometers should be 100 ppm/
°C
or less. The 3.9 M
and 10 M resistors (20% carbon or better)
should be located close to the ADDAC80 to prevent noise pickup.
If it is not convenient to use these high-value resistors, a function-
ally equivalent “T” network, as shown in Figure 8 may be
substituted in each case. The gain adjust (Pin 23) is a high
impedance point and a 0.01
F ceramic capacitor should be
connected from this pin to common to prevent noise pickup.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADDAC80N-CBI-V 制造商:Analog Devices 功能描述:SEMICONDUCTORSL
ADDAC80N-CBI-V/+ 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
ADDAC80NZ-CBI-V 功能描述:IC DAC 12-BIT BINARY MONO 24-DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準包裝:1 系列:- 設(shè)置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行,SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散(最大):- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC(0.154",3.90mm 寬) 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓,單極;1 電壓,雙極 采樣率(每秒):* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND
ADDAC80NZ-CBI-V 制造商:Analog Devices 功能描述:IC, DAC, 12BIT, DIP-24
ADDAC80Z-CBI-I 制造商:AD 制造商全稱:Analog Devices 功能描述:COMPLETE LOW COST 12-BIT D/A CONVERTERS