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參數(shù)資料
| 型號： | ADF4001BRU-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN PLL 16-TSSOP |
| 標準包裝： | 1,000 |
| 類型： | 時鐘發(fā)生器（RF） |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
REV.
ADF4001
–14–
COHERENT CLOCK GENERATION
When testing A/D converters, it is often advantageous to use a
coherent test system, that is, a system that ensures a specific
relationship between the A/D converter input signal and the
A/D converter sample rate. Thus, when doing an FFT on this
data, there is no longer any need to apply the window weighting
function. Figure 8 shows how the ADF4001 can be used to handle
all the possible combinations of the input signal frequency and
sampling rate. The first ADF4001 is phase locked to a VCO. The
output of the VCO is also fed into the N divider of the second
ADF4001. This results in both ADF4001s being coherent with
the REFIN. Since the REFIN comes from the signal generator, the
MUXOUT signal of the second ADF4001 is coherent with the fIN
frequency to the ADC. This is used as fS, the sampling clock.
CPRF
REFIN
f
S
= (f
IN
N1)/(R1
N2)
A/D
CONVERTER
UNDER
TEST
ADF4001
SINE
OUTPUT
BRUEL &
KJAER
MODEL 1051
SQUARE
OUTPUT
VCO
100MHz
LOOP
FILTER
RFIN
MUXOUT
NC7S04
N2
N1
R1
fIN
fS
SAMPLING
CLOCK
AIN
Figure 8. Coherent Clock Generator
TRI-BAND CLOCK GENERATION CIRCUIT
In multiband applications, it is necessary to realize different
clocks from one master clock frequency. For example, GSM
uses a 13 MHz system clock, WCDMA uses 19.44 MHz, and
CDMA uses 19.2 MHz. The circuit in Figure 9 shows how to
use the ADF4001 to generate GSM, WCDMA, and CDMA
system clocks from a single 52 MHz master clock. The low RF
fMIN specification and the ability to program R and N values as
low as
1 makes the ADF4001 suitable for this. Other fOUT
clock frequencies can be realized using the formula
f
REF
N
R
OUT
IN
=×
÷
()
SHUTDOWN CIRCUIT
The circuit in Figure 10 shows how to shut down both the
ADF4001 and the accompanying VCO. The ADG702 switch
goes open circuit when a Logic 1 is applied to the IN input.
The low cost switch is available in both SOT-23 and micro
SOIC packages.
19.44MHz SYSTEM
CLOCK FOR WCDMA
19.2MHz SYSTEM
CLOCK FOR CDMA
13MHz SYSTEM
CLOCK FOR GSM
R2
1300
ADF4001
RFIN
REFIN
CPRF
65
R3
CPRF
ADF4001
REFIN
RFIN
R1
4
REFIN
RFIN
ADF4001
CPRF
52MHz
MASTER
CLOCK
N2
486
LOOP
FILTER
VCXO
19.44MHz
N1
1
N3
24
VCXO
13MHz
VCXO
19.2MHz
LOOP
FILTER
LOOP
FILTER
Figure 9. Tri-Band System Clock Generation
FREFIN
AGND
4
DGND
9
CPGND
3
ADF4001
RFINA
RFINB
100pF
51
AVDD
VDD
7
DVDD
15
VP
16
CE
10
1
2
RSET
CP
POWER-DOWN CONTROL
DECOUPLING CAPACITORS AND INTERFACE
SIGNALS HAVE BEEN OMITTED FROM THE
DIAGRAM IN THE INTEREST OF GREATER CLARITY.
6
5
10k
LOOP
FILTER
RFOUT
100pF
18
100pF
ADG702
S
D
GND
VDD
IN
VCC
GND
VCO
OR
VCXO
Figure 10. Local Oscillator Shutdown Circuit
B
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| ADF4001BRUZ | 功能描述:IC CLOCK GEN PLL 16-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
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