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參數(shù)資料
| 型號： | ADF4001BRUZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 1/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN PLL 200MHZ 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時鐘發(fā)生器（RF） |
| PLL： | 是 |
| 輸入： | 時鐘 |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax:
Analog Devices, Inc. All rights reserved.
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
REV.
200 MHz Clock Generator PLL
FUNCTIONAL BLOCK DIAGRAM
RFINA
RFINB
13-BIT
N COUNTER
LOCK DETECT
CURRENT
SETTING 1
CPI3
CPI2
CPI1 CPI6 CPI5
CPI4
M1
M3
M2
SDOUT
AVDD
REFIN
CLK
DATA
LE
AVDD
DVDD
VP
CPGND
RSET
14-BIT
R COUNTER
LATCH
FUNCTION
LATCH
24-BIT
INPUT REGISTER
N COUNTER
LATCH
SDOUT
22
14
ADF4001
MUXOUT
MUX
HIGH Z
CURRENT
SETTING 2
CHARGE
PUMP
CP
CE
AGND
DGND
PHASE
FREQUENCY
DETECTOR
REFERENCE
13
FEATURES
200 MHz Bandwidth
2.7 V to 5.5 V Power Supply
Separate Charge Pump Supply (VP) Allows Extended
Tuning Voltage in 5 V Systems
Programmable Charge Pump Currents
3-Wire Serial Interface
Hardware and Software Power-Down Mode
Analog and Digital Lock Detect
Hardware Compatible to the ADF4110/ADF4111/
ADF4112/ADF4113
Typical Operating Current 4.5 mA
Ultralow Phase Noise
16-Lead TSSOP
20-Lead LFCSP
APPLICATIONS
Clock Generation
Low Frequency PLLs
Low Jitter Clock Source
Clock Smoothing
Frequency Translation
SONET, ATM, ADM, DSLAM, SDM
GENERAL DESCRIPTION
The ADF4001 clock generator can be used to implement clock
sources for PLLs that require very low noise, stable reference
signals. It consists of a low noise digital PFD (phase frequency
detector), a precision charge pump, a programmable reference
divider, and a programmable 13-bit N counter. In addition, the
14-bit reference counter (R counter) allows selectable REFIN
frequencies at the PFD input. A complete PLL (phase-locked
loop) can be implemented if the synthesizer is used with an exter-
nal loop filter and VCO (voltage controlled oscillator) or
VCXO (voltage controlled crystal oscillator). The N minimum
value of 1 allows flexibility in clock generation.
2013
781/461-3113
B
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4001BRUZ-RL | 功能描述:IC CLOCK GEN PLL 200MHZ 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4001SP1BRU | 制造商:Analog Devices 功能描述:- Rail/Tube |
| ADF4001SP1BRU-RL7 | 制造商:Analog Devices 功能描述: |
| ADF4001SP1BRUZ | 制造商:Analog Devices 功能描述: |
| ADF4001SP1BRUZ-RL7 | 制造商:Analog Devices 功能描述: |
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