參數(shù)資料
型號: ADF4002BRUZ-RL7
廠商: Analog Devices Inc
文件頁數(shù): 11/20頁
文件大?。?/td> 0K
描述: IC PLL FREQUENCY SYNTH 16-TSSOP
設(shè)計(jì)資源: Very Low Jitter Encode (Sampling) Clocks for High Speed Analog-to-Digital Converters Using ADF4002 (CN0003)
標(biāo)準(zhǔn)包裝: 1,000
類型: 時鐘/頻率合成器(RF),相位檢測器
PLL:
輸入: CMOS,TTL
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 2:1
差分 - 輸入:輸出: 是/無
頻率 - 最大: 400MHz
除法器/乘法器: 是/無
電源電壓: 2.7 V ~ 3.3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
配用: EVAL-ADF4002EBZ1-ND - BOARD EVAL FOR ADF4002
Data Sheet
ADF4002
Rev. C | Page 19 of 20
OUTLINE DIMENSIONS
16
9
8
1
PIN 1
SEATING
PLANE
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX
0.20
0.09
0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 24. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
3.75
BCS SQ
COMPLIANT
TO JEDEC STANDARDS MO-220-VGGD-1
1
0.50
BSC
PIN 1
INDICATOR
0.75
0.60
0.50
TOP VIEW
12° MAX
0.80 MAX
0.65 TYP
SEATING
PLANE
PIN 1
INDICATOR
COPLANARITY
0.08
1.00
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
2.25
2.10 SQ
1.95
20
6
16
10
11
15
5
0.60 MAX
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
04-
09-
2012-
B
BOTTOM VIEW
EXPOSED
PAD
4.10
4.00 SQ
3.90
Figure 25. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-20-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
ADF4002BRUZ
40°C to +85°C
16-Lead TSSOP
RU-16
ADF4002BRUZ-RL
40°C to +85°C
16-Lead TSSOP
RU-16
ADF4002BRUZ-RL7
40°C to +85°C
16-Lead TSSOP
RU-16
ADF4002BCPZ
40°C to +85°C
20-Lead LFCSP_VQ
CP-20-1
ADF4002BCPZ-RL
40°C to +85°C
20-Lead LFCSP_VQ
CP-20-1
ADF4002BCPZ-RL7
40°C to +85°C
20-Lead LFCSP_VQ
CP-20-1
EV-ADF4002SD1Z
Evaluation Board
EV-ADF411XSD1Z
Evaluation Board
1
Z = RoHS Compliant Part.
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