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參數(shù)資料
| 型號(hào)： | ADF4106BRUZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/24頁 |
| 文件大小： | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 16TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘/頻率合成器，RF |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 6GHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 配用： | EVAL-ADF4106EBZ1-ND - BOARD EVAL FOR ADF4106 |
Data Sheet
ADF4106
Rev. E | Page 7 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
02720-003
RSET
CP
CPGND
AGND
1
2
3
4
5
6
7
8
RFINB
RFINA
AVDD
REFIN
MUXOUT
LE
DATA
CLK
CE
DGND
16
15
14
13
12
11
10
9
VP
DVDD
TOP VIEW
(Not to Scale)
ADF4106
NOTE: TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).
Figure 3. 16-Lead TSSOP Pin Configuration
02720-
004
15 MUXOUT
14 LE
13 DATA
12 CLK
CPGND 1
AGND 2
AGND 3
20
C
P
11 CE
6
7
8
DG
ND
9
DG
ND
10
19
18
17
16
RFINB 4
RFINA 5
R
SET
V
P
DV
DD
DV
DD
PIN 1
INDICATOR
TOP VIEW
ADF4106
A
V
DD
A
V
DD
RE
F
IN
NOTES
1. TRANSISTOR COUNT 6425 (CMOS),
303 (BIPOLAR).
2. THE EXPOSED PAD MUST BE
CONNECTED TO AGND.
Figure 4. 20-Lead LFCSP_VQ Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
TSSOP
Pin No.
LFCSP
Mnemonic
Function
1
19
RSET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is
SET
MAX
CP
R
I
5
.
25
=
So, with RSET = 5.1 k, ICP MAX = 5 mA.
2
20
CP
Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn
drives the external VCO.
3
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
4
2, 3
AGND
Analog Ground. This is the ground return path of the prescaler.
5
4
RFINB
Complementary Input to the RF Prescaler. This point must be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF. See Figure 18.
6
5
RFINA
Input to the RF Prescaler. This small signal input is ac-coupled to the external VCO.
7
6, 7
AVDD
Analog Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD.
8
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input
resistance of 100 k. See Figure 18. This input can be driven from a TTL or CMOS crystal oscillator or
it can be ac-coupled.
9
9, 10
DGND
Digital Ground.
10
11
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output
into three-state mode. Taking the pin high powers up the device, depending on the status of the
power-down bit, F2.
11
12
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched
into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.
12
13
DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits.
This input is a high impedance CMOS input.
13
14
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one
of the four latches with the latch being selected using the control bits.
14
15
MUXOUT
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency
to be accessed externally.
15
16, 17
DVDD
Digital Power Supply. This may range from 2.7 V to 3.3 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
16
18
VP
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V,
it can be set to 5.5 V and used to drive a VCO with a tuning range of up to 5 V.
EP
Exposed Pad. The exposed pad must be connected to AGND.
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