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參數(shù)資料
| 型號： | ADF4106SCPZ-EP-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 20LFCSP |
| 標準包裝： | 1,500 |
| 類型： | 頻率合成器 |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 6GHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 20-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
ADF4106-EP
Data Sheet
Rev. B | Page 4 of 12
Parameter
BVersion1
Unit
Test Conditions/Comments
NOISE CHARACTERISTICS
Normalized Phase Noise Floor (PN
SYNTH)
223
dBc/Hz typ
PLL loop BW = 500 kHz
Normalized 1/f Noise (PN
1_f)
122
dBc/Hz typ
Measured at 10 kHz offset; normalized to 1 GHz
Phase Noise Performance12
VCO output
900 MHz13
92.5
dBc/Hz typ
1 kHz offset and 200 kHz PFD frequency
5800 MHz14
76.5
dBc/Hz typ
1 kHz offset and 200 kHz PFD frequency
5800 MHz15
83.5
dBc/Hz typ
1 kHz offset and 1 MHz PFD frequency
Spurious Signals
900 MHz13
90/92
dBc typ
200 kHz/400 kHz and 200 kHz PFD frequency
5800 MHz14
65/70
dBc typ
200 kHz/400 kHz and 200 kHz PFD frequency
5800 MHz15
70/75
dBc typ
1 MHz/2 MHz and 1 MHz PFD frequency
1 Operating temperature range is 55°C to +125°C.
2 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
3 AV
DD = DVDD = 3 V.
4 AC coupling ensures AV
DD/2 bias.
5 Guaranteed by design. Sample tested to ensure compliance.
6 T
A = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 900 MHz.
7 T
A = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 2.0 GHz.
8 T
A = 25°C; AVDD = DVDD = 3 V; P = 32; RFIN = 6.0 GHz.
9 T
A = 25°C; AVDD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RFIN = 6.0 GHz.
10 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log FPFD. PNSYNTH = PNTOT 10 log FPFD 20 log N.
11 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, f
RF, and at a
frequency offset, f, is given by PN = P1_f + 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
12 The phase noise is measured with the EVAL-ADF4106-EB1 evaluation board and the Agilent E4440A spectrum analyzer. The spectrum analyzer provides the REF
IN for
the synthesizer (fREFOUT = 10 MHz @ 0 dBm).
13 f
REFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop B/W = 20 kHz.
14 f
REFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 5800 MHz; N = 29,000; loop B/W = 20 kHz.
15 f
REFIN = 10 MHz; fPFD = 1 MHz; offset frequency = 1 kHz; fRF = 5800 MHz; N = 5800; loop B/W = 100 kHz.
TIMING CHARACTERISITICS
AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 k, dBm referred to 50 , TA = TMAX to TMIN,
unless otherwise noted.
Table 2.
Parameter
Limit1 (B Version)
Unit
Test Conditions/Comments
t
1
10
ns min
DATA to CLOCK Setup Time
t
2
10
ns min
DATA to CLOCK Hold Time
t
3
25
ns min
CLOCK High Duration
t
4
25
ns min
CLOCK Low Duration
t
5
10
ns min
CLOCK to LE Setup Time
t
6
20
ns min
LE Pulse Width
1 Operating temperature range (B Version) is –40°C to +85°C.
Timing Diagram
CLOCK
DB22
DB2
DATA
LE
t1
LE
DB23 (MSB)
t2
DB1 (CONTROL
BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t3
t4
t6
t5
09272-
002
Figure 2. Timing Diagram
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