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參數(shù)資料
| 型號： | ADF4206BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | Dual RF PLL Frequency Synthesizers |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 550 MHz, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 206K |
| 代理商： | ADF4206BRU |
REV. 0
ADF4206/ADF4207/ADF4208
TIMING CHARACTERISTICS
–4–
Limit at
T
MIN
to T
MAX
(B Version)
Parameter
Unit
Test Conditions/Comments
t
1
t
2
t
3
t
4
t
5
t
6
10
10
25
25
10
20
ns min
ns min
ns min
ns min
ns min
ns min
DATA to CLOCK Setup Time
DATA to CLOCK Hold Time
CLOCK High Duration
CLOCK Low Duration
CLOCK to LE Setup Time
LE Pulsewidth
NOTES
Guaranteed by design but not production tested.
Specification subject to change without notice.
(V
DD
1 = V
DD
2 = 3 V 10%, 5 V 10%; V
DD
1, V
DD
2
≤
V
P
1, V
P
2
≤
6.0 V; AGND
RF1
= DGND
RF1
=
AGND
RF2
= DGND
RF2
= 0 V; T
A
= T
MIN
to T
MAX
unless otherwise noted, dBm referred to 50
.)
DB0 (LSB)
(CONTROL BIT C1)
CLOCK
DB21 (MSB)
DB20
DB2
DATA
LE
LE
t
3
t
4
t
2
t
5
t
1
t
6
DB1
(CONTROL BIT C2)
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS
1, 2
(T
A
= 25
°
C unless otherwise noted.)
V
DD
1 to GND
3
. . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
DD
1 to V
DD
2 . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
V
P
1, V
P
2 to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
P
1, V
P
2 to V
DD
1 . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V
Digital I/O Voltage to GND . . . . . . –0.3 V to DV
DD
+ 0.3 V
Analog I/O Voltage to GND . . . . . . . . . –0.3 V to V
P
+ 0.3 V
OSC
IN
, OSC
OUT
, RF1
IN
(A, B),
RF2
IN
(A, B) to GND . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
RF
IN
A to RF
IN
B (RF1, RF2) . . . . . . . . . . . . . . . . . .
±
320 mV
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40
°
C to +85
°
C
Storage Temperature Range . . . . . . . . . . . . –65
°
C to +150
°
C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150
°
C
TSSOP
θ
JA
Thermal Impedance . . . . . . . . . . . . . 150.4
°
C/W
CSP
θ
JA
(Paddle Soldered) . . . . . . . . . . . . . . . . . . . 122
°
C/W
CSP
θ
JA
(Paddle Not Soldered) . . . . . . . . . . . . . . . . 216
°
C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215
°
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
°
C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
This device is a high-performance RF integrated circuit with an ESD rating of
< 2 kV and it is ESD sensitive. Proper precautions should be taken for handling
and assembly.
3
GND = AGND = DGND = 0 V.
TRANSISTOR COUNT
11749 (CMOS) and 522 (Bipolar).
ORDERING GUIDE
Model
Temperature Range
–40
°
C to +85
°
C
–40
°
C to +85
°
C
–40
°
C to +85
°
C
Package Description
Package Option
*
ADF4206BRU
ADF4207BRU
ADF4208BRU
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
RU-16
RU-16
RU-20
*
Contact the factory for chip availability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADF4206/ADF4207/ADF4208 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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