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參數(shù)資料
| 型號(hào)： | ADF4218LBRUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 20TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘/頻率合成器（RF/IF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 3GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.6 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 帶卷 (TR) |
REV. C
ADF4217L/ADF4218L/ADF4219L
–20–
SPI COMPATIBLE SERIAL BUS
LOCK
DETECT
VCO190-1068U
VCC
CPIF
IFIN
REFIN
DGND
RF
A
GND
RF
DGND
IF
A
GND
IF
CLK
DATA
LE
RFIN
MUXOUT
CPRF
VP1
VP2VDD2VDD1
ADF4217L/
ADF4218L/
ADF4219L
VCO190-125T
VCC
10MHz
TCXO
DECOUPLING CAPACITORS (22 F/10pF) ON VDD, VP OF THE ADF4217L/ADF4218L/ADF4219L.
THE TCXO AND ON VCC OF THE VCOs HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
400pF
620pF
3.9nF
100pF
620pF
6nF
620pF
100pF
3.3k
18
51
9k
18
51
3.3k
RFOUT
VP
VDD
VP
IFOUT
5.8k
VDD
Figure 7. Local Oscillator Design for GSM Receiver
RF Program Modes
Tables IV and VII show how to set up the RF program modes.
RF Charge Pump Currents
P13 sets the RF charge pump current. With P13 set to “0,” ICP is
1.0 mA. With P13 set to “1,” ICP is 4.0 mA. See Table VII.
Programmable RF AB Counter
If control bits C2, C1 are 1, 1, the data in the input register is used
to program the RF AB counter. For the ADF4217L/ADF4218L,
the AB counter consists of a 6-bit swallow counter (A counter)
and 11-bit programmable counter (B counter). Table VIII shows
the input register data format for programming the RF AB counter
and the possible divide ratios. The ADF4219L N counter consists
of a 13-bit B counter and 5-bit A counter. Table IX shows the
input register data format for programming the ADF4219L.
RF Prescaler Value
P14 in the RF AB counter latch sets the RF prescaler value. For
the ADF4217L and ADF4218L family, 32/33 or 64/65 prescalers
are available. See Table VIII. For the ADF4219L, the prescaler
may be 16/17 or 32/33. See Table IX.
RF Power-Down
Tables VII, VIII, and IX show the power-down bits (Charge
Pump Bit used for asynchronous in the ADF4217L family). See
the Power-Down section for a functional description.
RF Fastlock
The RF CP Gain Bit (P13) of the RF N Register in the ADF4217L
family is the Fastlock Enable Bit. The loop filter should be
designed for the lower current setting. When Fastlock is enabled,
the RF CP current is set to maximum value. Also, an extra loop
filter damping resistor to ground is switched in using the
MUXOUT pin, thus compensating for the change of loop
dynamics when in Fastlock Mode. Since the RF CP Gain Bit is
contained in the RF N counter, only one write is needed to
program the new frequency and to initiate Fastlock. To come
out of Fastlock, the RF CP Gain Bit should be returned to “0”
and the extra damping resistor switched out.
APPLICATIONS SECTION
Local Oscillator for GSM Handset Receiver
The diagram in Figure 7 shows the ADF4217L/ADF4218L/
ADF4219L being used in a classic superheterodyne receiver to
provide the required LOs (local oscillators). In this circuit, the
reference input signal is applied to the circuit at fREF
IN and is
being generated by a 13 MHz temperature controlled crystal
oscillator. In order to have a channel spacing of 200 kHz (the GSM
standard), the reference input must be divided by 65, using the
on-chip reference counter.
The RF output frequency range is 1050 MHz to 1085 MHz.
Loop filter component values are chosen so that the loop band-
width is 20 kHz. The synthesizer is set up for a charge pump
current of 4.0 mA, and the VCO sensitivity is 15.6 MHz/V.
The IF output is fixed at 125 MHz. The IF loop bandwidth is
chosen to be 20 kHz with a channel spacing of 200 kHz. Loop
filter component values are chosen accordingly.
Local Oscillator for WCDMA Receiver
Figure 8 shows the ADF4217L/ADF4218L/ADF4219L being
used to generate the local oscillator frequencies in a wideband
CDMA (WCDMA) system.
The RF output range needed is 1720 MHz to 1780 MHz. The
VCO190-1750T from Varil-L will accomplish that. Channel spacing
is 200 kHz, the loop bandwidth of the loop filter is 20 kHz, and the
VCO sensitivity is 32 MHz/V. A charge pump current of 4.0 mA
is used and the desired phase margin for the loop is 45 degrees.
The IF output is fixed at 200 MHz. The VCO190-200T is used.
It has a sensitivity of 11.5 MHz/V. Channel spacing and loop
bandwidth are chosen the same as the RF side.
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| ADF4218LBRUZ-REEL7 | 功能描述:IC PLL FREQ SYNTHESIZER 20TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時(shí)鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4219L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ADF4217L/18L/19L: Dual Low Power Frequency Synthesizers Data Sheet (Rev. B. 7/02) |
| ADF4219LBCC | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual Up to 188MHz 24-Pin LGA |
| ADF4219LBCC-REEL | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual Up to 188MHz 24-Pin LGA T/R |
| ADF4219LBCC-REEL7 | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Dual Up to 188MHz 24-Pin LGA T/R |
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