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參數(shù)資料
| 型號： | ADF4360-3BCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER VCO 24LFCSP |
| 標準包裝： | 5,000 |
| 類型： | 扇出配送，整數(shù)-N，合成器（RF） |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 1.95GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 帶卷 (TR) |
ADF4360-3
Data Sheet
Rev. D | Page 22 of 24
PCB DESIGN GUIDELINES FOR CHIP SCALE PACKAGE
The leads on the chip scale package (CP-24) are rectangular.
The printed circuit board pad for these should be 0.1 mm long-
er than the package lead length and 0.05 mm wider than the
package lead width. The lead should be centered on the pad to
ensure that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern to ensure that short-
ing is avoided.
Thermal vias may be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at a
1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm, and the via barrel should be plated with 1 ounce
of copper to plug the via.
The user should connect the printed circuit thermal pad to
AGND. This is internally connected to AGND.
OUTPUT MATCHING
There are a number of ways to match the output of the
ADF4360-3 for optimum operation; the most basic is to use a
50 resistor to VVCO. A dc bypass capacitor of 100 pF is con-
nected in series, as shown Figure 21. Because the resistor is not
frequency dependent, this provides a good broadband match.
The output power in this circuit typically gives 3 dBm output
power into a 50 load.
100pF
04437-025
RFOUT
VVCO
50
51
Figure 21. Simple ADF4360-3 Output Stage
A better solution is to use a shunt inductor (acting as an RF
choke) to VVCO. This gives a better match and therefore more
output power. Additionally, a series inductor is added after the
dc bypass capacitor to provide a resonant LC circuit. This tunes
the oscillator output and provides approximately 10 dB addi-
tional rejection of the second harmonic. The shunt inductor
needs to be a relatively high value (>40 nH).
Experiments have shown that the circuit shown in Figure 22
provides an excellent match to 50 over the operating range of
the ADF4360-3. This gives approximately 2 dBm output pow-
er across the frequency range of the ADF4360-3. Both single-
ended architectures can be examined using the EV-ADF4360-
3EB1Z evaluation board.
4.3nH
47nH
2.7pF
04437-026
RFOUT
VVCO
50
Figure 22. Optimum ADF4360-3 Output Stage
If the user does not need the differential outputs available on
the ADF4360, the user may either terminate the unused output
or combine both outputs using a balun. The circuit in Figure 23
shows how best to combine the outputs.
2.4nH
3.9nH
47nH
3.9nH
1.8pF
10pF
1.8pF
50
2.4nH
RFOUTA
VVCO
RFOUTB
04437-027
Figure 23. Balun for Combining ADF4360-3 RF Outputs
The circuit in Figure 23 is a lumped-lattice-type LC balun. It is
designed for a center frequency of 1.8 GHz and outputs 3.0 dBm
at this frequency. The series 2.4 nH inductor is used to tune out
any parasitic capacitance due to the board layout from each
input, and the remainder of the circuit is used to shift the
output of one RF input by +90° and the second by 90°, thus
combining the two. The action of the 3.9 nH inductor and the
1.8 pF capacitor accomplish this. The 47 nH is used to provide
an RF choke in order to feed the supply voltage, and the 10 pF
capacitor provides the necessary dc block. To ensure good RF
performance, the circuits in Figure 22 and Figure 23 were
implemented with Coilcraft 0402/0603 inductors and AVX 0402
thin-film capacitors.
Alternatively, instead of the LC balun shown in Figure 23, both
outputs may be combined using a 180° rat-race coupler.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| ADF4360-3BCPZRL7 | 功能描述:IC SYNTHESIZER VCO 24LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應商設備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4360-4 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MHz to 6 GHz Broadband Quadrature Modulator |
| ADF4360-4BCP | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 24-Pin LFCSP EP 制造商:Analog Devices 功能描述:IC SYNTHESIZER PLL |
| ADF4360-4BCPRL | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 24-Pin LFCSP EP T/R |
| ADF4360-4BCPRL7 | 制造商:Analog Devices 功能描述:PLL Frequency Synthesizer Single 24-Pin LFCSP EP T/R |
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