RON Ohmic resistance between D and S.
參數(shù)資料
型號(hào): ADG451BNZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 3/16頁(yè)
文件大?。?/td> 0K
描述: IC SWITCH QUAD SPST 16DIP
產(chǎn)品培訓(xùn)模塊: iCMOS™ Switches and Multiplexers for Data Acquisition
Switch Fundamentals
標(biāo)準(zhǔn)包裝: 25
系列: LC²MOS
功能: 開關(guān)
電路: 4 x SPST - NC
導(dǎo)通狀態(tài)電阻: 8 歐姆
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 12V,±15V
電流 - 電源: 100pA
工作溫度: -40°C ~ 85°C
安裝類型: 通孔
封裝/外殼: 16-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 16-PDIP
包裝: 管件
產(chǎn)品目錄頁(yè)面: 800 (CN2011-ZH PDF)
ADG451/ADG452/ADG453
Rev. C | Page 11 of 16
TERMINOLOGY
RON
Ohmic resistance between D and S.
ΔRON
On resistance match between any two channels, that is, RON
maximum minus RON minimum.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.
IS (OFF)
Source leakage current with the switch off.
ID (OFF)
Drain leakage current with the switch off.
ID, IS (ON)
Channel leakage current with the switch on.
VD (VS)
Analog voltage on Terminal D and Terminal S.
CS (OFF)
Off switch source capacitance.
CD (OFF)
Off switch drain capacitance.
CD (ON), CS (ON)
On switch capacitance.
tON
Delay between applying the digital control input and the output
switching on. See Figure 19.
tOFF
Delay between applying the digital control input and the output
switching off.
tD
Off time or on time measured between the 90% points of both
switches, when switching from one address state to another. See
Crosstalk
A measure of unwanted signal coupled through from one
channel to another as a result of parasitic capacitance.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
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