參數資料
型號: ADG451BRZ-REEL7
廠商: Analog Devices Inc
文件頁數: 4/16頁
文件大?。?/td> 0K
描述: IC SWITCH QUAD SPST 16SOIC
產品培訓模塊: Switch Fundamentals
標準包裝: 1,000
系列: LC²MOS
功能: 開關
電路: 4 x SPST - NC
導通狀態(tài)電阻: 8 歐姆
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 12V,±15V
電流 - 電源: 100pA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 16-SOIC
包裝: 帶卷 (TR)
ADG451/ADG452/ADG453
Rev. C | Page 12 of 16
APPLICATIONS
Figure 15 illustrates a precise, fast, sample-and-hold circuit. An
AD845 is used as the input buffer, and the output operational
amplifier is an AD711. During track mode, SW1 is closed, and
the output, VOUT, follows the input signal, VIN. In hold mode,
SW1 is opened, and the signal is held by the hold capacitor, CH.
SD
VOUT
SD
–15V
+15V
+5V
CC
1000pF
2200pF
RC
75
12
13
4
5
SW1
ADG451/
ADG452/
ADG453
–15V
+15V
VIN
AD845
–15V
+15V
AD711
SW2
CH
2200pF
05
23
9-
0
13
Figure 15. Fast, Accurate Sample-and-Hold Circuit
Due to switch and capacitor leakage, the voltage on the hold
capacitor decreases with time. The ADG451/ADG452/ADG453
minimize this droop due to their low leakage specifications. The
droop rate is further minimized by the use of a polystyrene
hold capacitor. The droop rate for the circuit shown is typically
30 μV/μs.
A second switch, SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Because both
switches are at the same potential, they have a differential effect
on the op amp, AD711, which minimizes charge injection
effects. Pedestal error is also reduced by the compensation
network, RC and CC. This compensation network reduces the
hold time glitch while optimizing the acquisition time. Using
the illustrated op amps and component values, the pedestal
error has a maximum value of 5 mV over the ±10 V input
range. Both the acquisition and settling times are 850 ns.
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