參數(shù)資料
型號: ADG5213BRUZ-RL7
廠商: Analog Devices Inc
文件頁數(shù): 9/20頁
文件大?。?/td> 0K
描述: IC SWITCH SPST QUAD 16TSSOP
標(biāo)準(zhǔn)包裝: 1,000
功能: 開關(guān)
電路: 4 x SPST - NC/NO
導(dǎo)通狀態(tài)電阻: 170 歐姆
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 9 V ~ 40 V,±9 V ~ ±22 V
電流 - 電源: 80µA
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
ADG5212/ADG5213
Rev. 0 | Page 17 of 20
TRENCH ISOLATION
In the ADG5212 and ADG5213, an insulating oxide layer
(trench) is placed between the NMOS and the PMOS transistors
of each CMOS switch. Parasitic junctions, which occur between
the transistors in junction isolated switches, are eliminated, and
the result is a completely latch-up proof switch.
In junction isolation, the N and P wells of the PMOS and NMOS
transistors form a diode that is reverse-biased under normal
operation. However, during overvoltage conditions, this diode
can become forward-biased. A silicon controlled rectifier (SCR)
type circuit is formed by the two transistors, causing a significant
amplification of the current that, in turn, leads to latch-up. With
trench isolation, this diode is removed and the result is a latch-
up proof switch.
NMOS
PMOS
PWELL
N WELL
BURIED OXIDE LAYER
HANDLE WAFER
TRENCH
09
76
7-
02
2
Figure 32. Trench Isolation
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