VDD = 5 V, V
參數(shù)資料
型號: ADG633YRU
廠商: Analog Devices Inc
文件頁數(shù): 11/16頁
文件大小: 0K
描述: IC SWITCH TRIPLE SPDT 16TSSOP
產(chǎn)品培訓模塊: Switch Fundamentals
標準包裝: 96
功能: 開關
電路: 3 x SPDT - NC/NO
導通狀態(tài)電阻: 150 歐姆
電壓電源: 單/雙電源
電壓 - 電源,單路/雙路(±): 2 V ~ 12 V,±2 V ~ 6 V
電流 - 電源: 10nA
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 16-TSSOP
包裝: 管件
ADG633
Rev. A | Page 4 of
16
SINGLE-SUPPLY OPERATION
VDD = 5 V, VSS = 0 V, GND = 0 V, TA = 40°C to +125°C, unless otherwise noted.
Table 2.
B Version
Y Version
Parameter
+25°C
40°C to +85°C
40°C to +125°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 to VDD
V
VDD = 4.5 V, VSS = 0 V
On Resistance, RON
85
Ω typ
VS = 0 V to 4.5 V, IS = 1 mA; see Figure 20
150
160
200
Ω max
VS = 0 V to 4.5 V, IS = 1 mA; see Figure 20
On-Resistance Match
Between Channels, ΔRON
4.5
Ω typ
VS = +3.5 V, IS = 1 mA
8
9
10
Ω max
VS = +3.5 V, IS = 1 mA
On-Resistance Flatness, RFLAT(ON)
13
14
16
Ω typ
VDD = 5 V, VSS = 0 V, VS = 1.5 V to 4 V, IS = 1 mA
LEAKAGE CURRENTS
VDD = 5.5 V
Source Off Leakage, IS(OFF)
±0.005
nA typ
VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 21
±0.2
±5
nA max
VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 21
Drain Off Leakage, ID(OFF)
±0.005
nA typ
VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 22
±0.2
±5
nA max
VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 22
Channel On Leakage, ID(ON), IS(ON)
±0.005
nA typ
VS = VD = 1 V or 4.5 V; see Figure 23
±0.2
±5
nA max
VS = VD = 1 V or 4.5 V; see Figure 23
DIGITAL INPUTS
Input High Voltage, VINH
2.4
V min
Input Low Voltage, VINL
0.8
V max
Input Current, IINL or IINH
0.005
μA typ
VIN = VINL or VINH
±1
μA max
VIN = VINL or VINH
Digital Input Capacitance, CIN
2
pF typ
DYNAMIC CHARACTERISTICS1
tTRANSITION
100
ns typ
RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 24
150
190
220
ns max
RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 24
tON (EN)
100
ns typ
RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26
150
190
220
ns max
RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26
tOFF (EN)
25
ns typ
RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26
35
45
50
ns max
RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26
Break-Before-Make Time Delay, tBBM
90
ns typ
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3 V; see Figure 25
10
ns min
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3 V; see Figure 25
Charge Injection
0.5
pC typ
VS = 2.5 V, RS = 0 Ω, CL = 1 nF; see Figure 27
1
pC max
VS = 2.5 V, RS = 0 Ω, CL = 1 nF; see Figure 27
Off Isolation
90
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
Channel-to-Channel Crosstalk
90
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 30
3 dB Bandwidth
520
MHz typ
RL = 50 Ω, CL = 5 pF; see Figure 29
CS(OFF)
5
pF typ
f = 1 MHz
CD(OFF)
8
pF typ
f = 1 MHz
CD(ON), CS(ON)
12
pF typ
f = 1 MHz
POWER REQUIREMENTS
VDD = 5.5 V
IDD
0.01
μA typ
Digital inputs = 0 V or 5.5 V
1
μA max
Digital inputs = 0 V or 5.5 V
1 Guaranteed by design; not subject to production test.
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