參數(shù)資料
型號(hào)： ADG738BRU-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/20頁(yè)
文件大?。?/td> 0K
描述： IC MUX/DEMUX 8X1 16TSSOP
產(chǎn)品培訓(xùn)模塊： Switch Fundamentals
產(chǎn)品變化通告： Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝： 2,500
功能： 多路復(fù)用器/多路分解器
電路： 1 x 8:1
導(dǎo)通狀態(tài)電阻： 4.5 歐姆
電壓電源： 單電源
電壓 - 電源，單路/雙路(±)： 2.7 V ~ 5.5 V
電流 - 電源： 10µA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 帶卷 (TR)
Data Sheet
ADG738/ADG739
Rev. A | Page 17 of 20
APPLICATIONS INFORMATION
EXPAND THE NUMBER OF SELECTABLE SERIAL
DEVICES USING AN ADG739
The dual 4-channel ADG739 multiplexer can be used to
multiplex a single chip select line to provide chip selects for
up to four devices on the SPI bus. Figure 30 illustrates the
ADG739 in such a typical configuration. All devices receive
the same serial clock and serial data, but only one device
receives the SYNC signal at any one time. The ADG739 is a
serially controlled device also. One bit programmable pin of
the microcontroller is used to enable the ADG739 via SYNC2,
while another bit programmable pin is used as the chip select
for the other serial devices, SYNC1. Driving SYNC2 low enables
changes to be made to the addressed serial devices. By
bringing SYNC1 low, the selected serial device hanging from
the SPI bus is enabled and data will be clocked into its input
shift register on the falling edges of SCLK. The convenient
design of the matrix switch allows for different combinations of
the four serial devices to be addressed at any one time. If more
devices need to be addressed via one chip select line, the
ADG738 is an 8-channel device and would allow further
expansion of the chip select scheme. There may be some digital
feedthrough from the digital input lines because SCLK and DIN
are permanently connected to each device. Using a burst clock
minimizes the effects of digital feedthrough on the analog
channels.
Figure 30. Addressing Multiple Serial Devices Using an ADG739
DAISY-CHAINING MULTIPLE ADG738S
A number of ADG738 matrix switches may be daisy-chained
simply by using the DOUT pin. DOUT is an open-drain output
that should be pulled to the supply with an external resistor.
Figure 31 shows a typical implementation. The SYNC pin of
all three parts in the example are tied together. When SYNC
is brought low, the input shift registers of all parts are enabled,
data is written to the parts via DIN, and clocked through the
shift registers. When the transfer is complete, SYNC is brought
high and all switches are updated simultaneously. Further shift
registers may be added in series.
Figure 31. Multiple ADG739 Devices in a Daisy-Chained Configuration
DA
1/2 OF
ADG739
VDD
SCLK
DIN
SYNC
S1A
S2A
S3A
S4A
SYNC1
DIN
SCLK
DIN
SCLK
DIN
SCLK
DIN
SCLK
DIN
SCLK
ADG739
ADG738
OTHER SPI
DEVICE
SYNC2
FROM
MICRO-
CONTROLLER
OR DSP
OTHER SPI
DEVICE
SYNC
10758-
023
SCLK
DIN
DOUT
ADG739
SCLK
DIN
ADG739
SCLK
DIN
T
U
O
D
T
U
O
D
SCLK
DIN
TO OTHER
SERIAL DEVICES
ADG739
VDD
R
SYNC
10758-
024
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