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參數(shù)資料
| 型號： | ADG739 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CMOS , Low Voltage, Serially Controlled Matrix Switches(CMOS,低電壓,串行控制四通道矩陣開關(guān)) |
| 中文描述： | 的CMOS，低電壓，串行控制矩陣開關(guān)（的CMOS，低電壓，串行控制四通道矩陣開關(guān)） |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 103K |
| 代理商： | ADG739 |
ADG738/ADG739
–7–
REV. PrC
Prelimnary Technical Data
DATA
TECHNCAL
G E NE R A L D E SC R IP T ION
T he ADG738 and ADG739 are serially controlled, 8
channel and dual 4 channel matrix switches respectively.
While providing the normal multiplexing and
demultiplexing functions, these parts also provide the user
with some more flexibility as to where their signal may be
routed. Each bit of the 8 bit serial word corresponds to
one switch of the part. A logic ‘1’ in the particular bit
position turns on the switch, while a logic ‘0’ turns the
switch off. Because each switch is independently control-
led by an individual bit, this provides the option of having
any, all or none of the switches ON. T his feature may be
particularly useful in the demultiplexing application where
the user may wish to direct one signal from the drain to a
number of outputs (sources). Care must be taken, how-
ever, in the multiplexing situation where a number of
inputs may be shorted together, (only separated by the
small on resistance of the switch).
POWE R ON RE SE T
On power up of the device, all switches will be in the
OFF condition and the internal shift register is filled with
zeros and will remain so until a valid write takes place.
S8
S7
S6
S5
S4
S3
S2
S1
DB0 (LSB)
DATA BITS
SE R IA L INT E R F A C E
T he ADG738 and ADG739 have a three wire serial inter-
face (
SYNC
, SCLK , and DIN), which is compatible with
SPI, QSPI, MICROWIRE interface standards and most
DSP’s. Figure 1 shows the timing diagram of a typical
write sequence.
Data is written to the 8-bit shift register via DIN under the
control of the
SYNC
and SCLK signals. Data may be
written to the shift register in more or less than 8 bits. In
each case the shift register retains the last eight bits that
were written.
When
SYNC
goes low, the input shift register is enabled.
Data from DIN is clocked into the shift register on the
falling edge of SCLK . Each bit of the eight bit word
corresponds to one of the eight switches. Figure 2 shows
the contents of the input shift register. Data appears on the
DOUT pin on the rising edge of SCLK suitable for daisy
chaining, delayed of course by eight bits. When all eight
bits have been written into the shift register, the
SYNC
line is brought high again. T he switches are updated with
the new configuration and the input shift register is
disabled. With
SYNC
held high, any further data or noise
on the DIN line will have no effect on the shift register.
Figure 2. Input Shift Register Contents
T E ST C IR C UIT S
T B D
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| ADG739BRU | 功能描述:IC MUX/DEMUX DUAL 4X1 16TSSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:- 其它有關(guān)文件:STG4159 View All Specifications 標(biāo)準(zhǔn)包裝:5,000 系列:- 功能:開關(guān) 電路:1 x SPDT 導(dǎo)通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:7-覆晶 包裝:帶卷 (TR) |
| ADG739BRU-REEL | 功能描述:IC MUX/DEMUX DUAL 4X1 16TSSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:- 標(biāo)準(zhǔn)包裝:48 系列:- 功能:開關(guān) 電路:4 x SPST - NO 導(dǎo)通狀態(tài)電阻:100 歐姆 電壓電源:單/雙電源 電壓 - 電源，單路/雙路(±):2 V ~ 12 V，±2 V ~ 6 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:管件 |
| ADG739BRU-REEL7 | 功能描述:IC MUX/DEMUX DUAL 4X1 16TSSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 功能:多路復(fù)用器 電路:1 x 4:1 導(dǎo)通狀態(tài)電阻:- 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±5V 電流 - 電源:7mA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR) |
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