參數(shù)資料
型號(hào)： ADG752BRMZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 4/9頁(yè)
文件大?。?/td> 0K
描述： IC VIDEO SWITCH SPDT 8MSOP
產(chǎn)品培訓(xùn)模塊： iCMOS™ Switches and Multiplexers for Data Acquisition
Switch Fundamentals
標(biāo)準(zhǔn)包裝： 50
功能： 視頻開(kāi)關(guān)
電路： 1 x SPDT - NC/NO
導(dǎo)通狀態(tài)電阻： 18 歐姆
電壓電源： 單電源
電壓 - 電源，單路/雙路(±)： 1.8 V ~ 5.5 V
電流 - 電源： 1nA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 803 (CN2011-ZH PDF)
ADG752
–4–
Table I. Truth Table
ADG752 IN
Switch S1
Switch S2
0
ON
OFF
1
OFF
ON
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG752 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
1
(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
Analog, Digital Inputs2 . . . . . . . . . . . . –0.3 V to VDD +0.3 V or
30 mA, Whichever Occurs First
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . .100 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40
°C to +85°C
Storage Temperature Range . . . . . . . . . . . . . –65
°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . (TJ Max–TA)/
θJA
Junction Temperature (TJ Max) . . . . . . . . . . . . . . . . . .+150
°C
SOIC Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 44°C/W
SOT-23 Package
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 229.6°C/W
θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 91.99°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +215
°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+220
°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability. Only one absolute maxi-
mum rating may be applied at any one time.
2Overvoltages at IN, S or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
TERMINOLOGY
VDD
Most positive power supply potential.
GND
Ground (0 V) reference.
S
Source terminal. May be an input or output.
D
Drain terminal. May be an input or output.
IN
Logic control input.
RON
Ohmic resistance between D and S.
RON
On resistance match between channels, i.e.,
RONmax–RONmin.
RFLAT(ON)
Flatness is defined as the difference between
the maximum and minimum value of on resis-
tance as measured over the specified analog
signal range.
IS (OFF)
Source leakage current with the switch “OFF.”
ID, IS (ON)
Channel leakage current with the switch “ON.”
VD (VS)
Analog voltage on terminals D and S.
CS (OFF)
“OFF” switch source capacitance.
CD, CS (ON)
“ON” switch capacitance.
tON
Delay between applying the digital control
input and the output switching on. See Test
Circuit 4.
tOFF
Delay between applying the digital control
input and the output switching off.
tD
“OFF” time or “ON” time measured between
the 90% points of both switches, when switch-
ing from one address state to another.
Off Isolation
A measure of unwanted signal coupling
through an “OFF” switch.
Crosstalk
A measure of unwanted signal that is coupled
through from one channel to another as a
result of parasitic capacitance.
Bandwidth
The frequency at which the output is attenu-
ated by –3 dBs.
On Response
The frequency response of the “ON” switch.
Insertion Loss
Loss due to the ON resistance of the switch.
VINL
Maximum input voltage for Logic “0.”
VINH
Minimum input voltage for Logic “1.”
IINL(IINH)
Input current of the digital input.
IDD
Positive supply current.
PIN CONFIGURATIONS
6-Lead SOT-23
(RT-6)
1
2
3
6
5
4
TOP VIEW
(Not to Scale)
ADG752
IN
D
VDD
S1
GND
S2
8-Lead
SOIC
(RM-8)
1
2
3
4
8
7
6
5
TOP VIEW
(Not to Scale)
NC = NO CONNECT
ADG752
NC
S1
D
VDD
S2
GND
IN
REV. A
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