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參數(shù)資料
| 型號： | ADG788BCP |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | 2.5ohm, 1.8V to 5.5V, +-2.5 V Triple/Quad SPDT Switches in Chip Scale Packages |
| 中文描述： | QUAD 1-CHANNEL, SGL POLE DOUBLE THROW SWITCH, QCC20 |
| 封裝： | 4 X 4 MM, CSP-20 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 144K |
| 代理商： | ADG788BCP |
REV. 0
ADG786/ADG788
–6–
T able I. ADG786 T ruth T able
A2
A1
A0
EN
ON Switch
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
1
0
0
0
0
0
0
0
0
None
D1-S1A, D2-S2A, D3-S3A
D1-S1B, D2-S2A, D3-S3A
D1-S1A, D2-S2B, D3-S3A
D1-S1B, D2-S2B, D3-S3A
D1-S1A, D2-S2A, D3-S3B
D1-S1B, D2-S2A, D3-S3B
D1-S1A, D2-S2B, D3-S3B
D1-S1B, D2-S2B, D3-S3B
T able II. ADG788 T ruth T able
Logic
Switch A
Switch B
0
1
OFF
ON
ON
OFF
V
DD
V
SS
Most Positive Power Supply Potential
Most Negative Power Supply in a Dual Supply Application. In single supply applications, this should be tied to
ground close to the device.
Positive Supply Current
Negative Supply Current
Ground (0 V) Reference
Source T erminal. May be an input or output
Drain T erminal. May be an input or output
Logic Control Input
Analog Voltage on T erminals D, S
Ohmic Resistance between D and S
On Resistance Match between Any T wo Channels, i.e., R
ON
max – R
ON
min.
Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured
over the specified analog signal range.
Source Leakage Current with the Switch “OFF”
Channel Leakage Current with the Switch “ON”
Maximum Input Voltage for Logic “0”
Minimum Input Voltage for Logic “1”
Input Current of the Digital Input
“OFF” Switch Source Capacitance. Measured with reference to ground.
“ON” Switch Capacitance. Measured with reference to ground.
Digital Input Capacitance
Delay time measured between the 50% and 90% points of the digital inputs and the switch “ON” condition.
Delay time measured between the 50% and 90% points of the digital input and the switch “OFF” condition.
Delay time between the 50% and 90% points of the
EN
digital input and the switch “ON” condition.
Delay time between the 50% and 90% points of the
EN
digital input and the switch “OFF” condition.
“OFF” time measured between the 80% points of both switches when switching from one address state to another.
A measure of the glitch impulse transferred Injection from the digital input to the analog output during switching.
A measure of unwanted signal coupling through an “OFF” switch.
A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic
capacitance.
T he Frequency Response of the “ON” Switch
T he Loss Due to the ON Resistance of the Switch.
I
DD
I
SS
GND
S
D
IN
V
D
(V
S
)
R
ON
R
ON
R
FLAT (ON)
I
S
(OFF)
I
D
, I
S
(ON)
V
INL
V
INH
I
INL
(I
INH
)
C
S
(OFF)
C
D
, C
S
(ON)
C
IN
t
ON
t
OFF
t
ON
(
EN
)
t
OFF
(
EN
)
t
OPEN
Charge
Off Isolation
Crosstalk
On Response
Insertion Loss
T E RMINOLOGY
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