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參數(shù)資料
| 型號： | ADG791GBCPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MUX/DEMUX QUAD 2X1 24LFCSP |
| 產(chǎn)品變化通告： | ADG79xx Discontinuance Notice 17/Aug/2010 |
| 標準包裝： | 1 |
| 功能： | 多路復用器/多路分解器 |
| 電路： | 4 x 2:1 |
| 導通狀態(tài)電阻： | 4 歐姆 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 3V，5V |
| 電流 - 電源： | 1nA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 800 (CN2011-ZH PDF) |
| 其它名稱： | ADG791GBCPZ-REELDKR |
ADG791A/ADG791G
Rev. 0 | Page 19 of 24
LDSW BIT
The LDSW bit allows the user to control the way the device
executes the commands loaded during the write operations.
The ADG791A/ADG791G executes all the commands loaded
between two successive write operations that have set the
LDSW bit high.
Setting the LDSW high for every write cycle ensures that the
device executes the command right after the LDSW bit was
loaded into the device. This setting can be used when the
desired configuration can be achieved by sending a single
command or when the switches and/or GPO pin are not
required to be updated at the same time. When the desired
configuration requires multiple commands with simultaneous
update, the LDSW bit should be set low while loading the
commands except the last one when the LDSW bit should be set
high. Once the last command with LDSW = high is loaded, the
device executes all commands received since the last update
simultaneously.
POWER ON/SOFTWARE RESET
The ADG791A/ADG791G has a software reset function
implemented by the RESETB bit from the second data byte
written to the device. For normal operation of the multiplexers
and GPO pin, this bit should be set high. When RESETB = low or
after power-up, the switches from all multiplexers are turned off
(open) and the GPO pin is set low.
READ OPERATION
When reading data back from the ADG791A/ADG791G, the
user must begin with an address byte and R/W bit. The switch
then acknowledges that it is prepared to transmit data by
pulling SDA low. Following this acknowledgement, the
ADG791A/ADG791G transmits two bytes on the next clock
edges. These bytes contain the status of the switches, and each
byte is followed by an acknowledge bit. A logic high bit
represents a switch in the on (close) state while a low represents
a switch in the off (open) state. For the GPO pin (ADG791G
only), the bit represents the logic value of the pin. Figure 32
illustrates the entire read sequence.
The bit maps accompanying Figure 32 show the relationship
between the elements of the ADG791A and ADG791G (that it,
the switches and GPO pins) and the bits that represent their
status after a completed read operation.
ADG791A Bit Map
RB15
RB14
RB13
RB12
RB11
RB10
RB9
RB8
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
S1A/D1
S1B/D1
S2A/D2
S2B/D2
S3A/D3
S3B/D3
S4A/D4
S4B/D4
-
ADG791G Bit Map
RB15
RB14
RB13
RB12
RB11
RB10
RB9
RB8
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
S1A/D1
S1B/D1
S2A/D2
S2B/D2
S3A/D3
S3B/D3
S4A/D4
S4B/D4
-
GPO1
-
SCL
SDA
A2
A1
A0
RB14
RB15
R/W
RB13 RB12 RB11 RB10 RB9 RB8
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
START
CONDITION
BY MASTER
STOP
CONDITION
BY MASTER
ADDRESS BYTE
ACKNOWLEDGE
BY SWITCH
ACKNOWLEDGE
BY SWITCH
ACKNOWLEDGE
BY SWITCH
06033
-032
Figure 32. ADG791A/ADG791G Read Operation
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