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參數(shù)資料
| 型號(hào)： | ADG793GBCPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 9/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MUX/DEMUX TRIPLE 3X1 24LFCSP |
| 產(chǎn)品變化通告： | ADG79xx Discontinuance Notice 17/Aug/2010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 功能： | 多路復(fù)用器/多路分解器 |
| 電路： | 3 x 3:1 |
| 導(dǎo)通狀態(tài)電阻： | 4 歐姆 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 3V，5V |
| 電流 - 電源： | 1nA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁(yè)面： | 801 (CN2011-ZH PDF) |
| 其它名稱： | ADG793GBCPZ-REELDKR |
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ADG793A/ADG793G
Rev. 0 | Page 17 of 24
THEORY OF OPERATION
The ADG793A/ADG793G are monolithic CMOS devices
comprising three 3:1 multiplexers/demultiplexers controllable
via a standard I2C serial interface. The CMOS process provides
ultralow power dissipation, yet gives high switching speed and
low on resistance.
The on-resistance profile is very flat over the full analog input
range, and the wide bandwidth ensures excellent linearity and
low distortion. These features, combined with a wide input
signal range make the ADG793A/ADG793G the ideal switching
solution for a wide range of TV applications.
The switches conduct equally well in both directions when on.
In the off condition, signal levels up to the supplies are blocked.
The integrated serial I2C interface controls the operation of the
multiplexers and general-purpose logic pins (ADG793G only).
The ADG793A/ADG793G has many attractive features, such as
the ability to individually control each multiplexer, the option of
reading back the status of any switch, and two general purpose
logic output pins controllable through the I2C interface. The
following sections describe these features in more detail.
I2C SERIAL INTERFACE
The ADG793A/ADG793G are controlled via an I2C-compatible
serial bus interface (refer to the I2C-Bus Specification available
from Philips Semiconductor) that allows the part to operate
as a slave device (no clock is generated by the ADG793A/
ADG793G). The communication protocol between the I2C
master and the device operates as follows.
1.
The master initiates data transfer by establishing a start
condition defined as a high-to-low transition on the SDA
line while SCL is high. This indicates that an address/data
stream follows. All slave devices connected to the bus
respond to the start condition and shift in the next eight
bits, consisting of a 7-bit address (MSB first) plus an R/W
bit. This bit determines the direction of the data flow
during the communication between the master and the
addressed slave device.
2.
The slave device whose address corresponds to the trans-
mitted address responds by pulling the SDA line low during
the ninth clock pulse (this is called the acknowledge bit).
At this stage, all other devices on the bus remain idle while
the selected device waits for data to be written to, or read
from, its serial register. If the R/W bit is set high, the
master reads from the slave device. However, if the R/W bit
is set low, the master writes to the slave device.
3.
Data transmits over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during the
low period of the clock signal, SCL, and remain stable
during the high period of SCL, because a low-to-high
transition when the clock signal is high can be interpreted
as a stop event which ends the communication between the
master and the addressed slave device.
4.
After transferring all data bytes, the master establishes a
stop condition, defined as a low-to-high transition on the
SDA line while SCL is high. In write mode, the master pulls
the SDA line high during the tenth clock pulse to establish
a stop condition. In read mode, the master issues a no
acknowledge for the ninth clock pulse (the SDA line
remains high). The master brings the SDA line low before
the tenth clock pulse and then high during the tenth clock
pulse to establish a stop condition.
I2C ADDRESS
The ADG793A/ADG793G have a 7-bit I2C address. The four
most significant bits are internally hardwired and the last three
bits A0, A1, and A2 are user-adjustable. This allows the user to
connect up to eight ADG793As/ADG793Gs to the same bus.
The I2C bit map shows the configuration of the 7-bit address.
7-Bit I2C Address Bit Configuration
MSB
LSB
1
0
1
0
A2
A1
A0
WRITE OPERATION
When writing to the ADG793A/ADG793G, the user must
begin with an address byte and R/W bit, after which time the
switch acknowledges that it is prepared to receive data by
pulling SDA low. Data is loaded into the device as a 16-bit word
under the control of a serial clock input, SCL. Figure 31
illustrates the entire write sequence for the ADG793A/
ADG793G. The first data byte (AX7 to AX0) controls the status
of the switches and the LDSW and RESETB bits from the
second byte control the operation mode of the device. Table 6
shows a list of all commands supported by the ADG793A/
ADG793G with the corresponding byte that needs to be loaded
during a write operation.
To achieve the desired configuration, one or more commands
can be loaded into the device. Any combination of the
commands in Table 6 can be used with these restrictions:
Only one switch from a given multiplexer can be on at any
given time.
When a sequence of successive commands affect the same
element (that is, the switch or GPO pin), only the last
command is executed.
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| ADG794BRQZ | 功能描述:IC MUX/DEMUX QUAD 2X1 16QSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開(kāi)關(guān)，多路復(fù)用器，多路分解器 系列:- 應(yīng)用說(shuō)明:Ultrasound Imaging Systems Application Note 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- 功能:開(kāi)關(guān) 電路:單刀單擲 導(dǎo)通狀態(tài)電阻:48 歐姆 電壓電源:單電源 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V 電流 - 電源:5µA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:48-LQFP 供應(yīng)商設(shè)備封裝:48-LQFP（7x7） 包裝:托盤 |
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