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參數(shù)資料
| 型號： | ADJD-S371-QR999 |
| 廠商： | Avago Technologies Ltd. |
| 英文描述： | Miniature Surface-Mount RGB Digital Color Sensor Module |
| 中文描述： | 微型表面貼裝RGB數(shù)字色彩傳感器模塊 |
| 文件頁數(shù)： | 22/23頁 |
| 文件大?。?/td> | 270K |
| 代理商： | ADJD-S371-QR999 |
8
The SCL clock line synchronizes the serial data transmis-
sion on the SDA data line. It is always generated by the
master. The frequency of the SCL clock line may vary
throughout the transmission as long as it still meets the
minimum timing requirements.
The master by default drives the SDA data line. The
slave drives the SDA data line only when sending an
acknowledge bit after the master writes data to the
slave or when the master requests the slave to send
data.
The SDA data line driven by the master may be
implemented on the negative edge of the SCL clock
line. The master may sample data driven by the slave on
the positive edge of the SCL clock line. Figure shows an
example of a master implementation and how the SCL
clock line and SDA data line can be synchronized.
Figure 5. Data bit synchronization
A complete data transfer is 8-bits long or -byte. Each
byte is sent most significant bit (MSB) first followed by
an acknowledge or not acknowledge bit. Each data
transfer can send an unlimited number of bytes
(depending on the data format).
Figure 6. Data byte transfer
SCL
SDA
SDA data sampled on the
positive edge of SCL
SDA data driven on the
negative edge of SCL
SDA
MSB
LSB
ACK
NO
ACK
SCL
S
or
Sr
P
Sr
or
P
1
2
8
9
1
2
8
9
START or repeated
START CONDITION
STOP or repeated
START CONDITION
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| ADJD-WD00 | 制造商:Avago Technologies 功能描述: |
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