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| 型號(hào)： | ADM1041AARQZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Secondary-Side Controller with Current Share and Housekeeping |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PDSO24 |
| 封裝： | LEAD FREE, MO-137AE, QSOP-24 |
| 文件頁(yè)數(shù)： | 8/56頁(yè) |
| 文件大?。?/td> | 991K |
| 代理商： | ADM1041AARQZ |
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ADM1041A
Parameter
DC Offset Trim Range (with Respect to Input)
DC Offset Trim Step Size
(with respect to input)
CURRENT SENSE CALIBRATION
Total Current Sense Error
2
(Gain and Offset)
Gain Range (I
SENSE
)
Gain Setting 1 (Reg 16h[2:0] = 000)
Gain Setting 2 (Reg 16h[2:0] = 001)
Gain Setting 3 (Reg 16h[2:0] = 010)
Gain Setting 4 (Reg 16h[2:0] = 100)
Gain Setting 5 (Reg 16h[2:0] = 101)
Gain Setting 6 (Reg 16h[2:0] = 110)
Full Scale (No Offset)
Attenuation Range
Current Share Trim Step (at SHRO)
Gain Accuracy
2, 4
, 40 mV at C
S
+, C
S
Rev. 0 | Page 8 of 56
Min
Typ
8
15
30
8
15
30
30
50
120
Max
Unit
mV
mV
mV
mV
mV
mV
μV
μV
μV
Test Conditions/Comments
Reg 17h[2:0] = 000. See Table 32 .
Reg 17h[2:0] = 001. See Table 32.
Reg 17h[2:0] = 010. See Table 32.
Reg 17h[2:0] = 100. See Table 32.
Reg 17h[2:0] = 101. See Table 32.
Reg 17h[2:0] = 110. See Table 32.
V
CM
= 2.0 V, V
DIFF
= 0 V
8 bits, 255 steps
Reg 15h[7:0]. See Table 30.
V
CSCM
= 2.0V, 0°C ≤ T
A
≤ 85
°
C,
SHRS = SHRO = 2 V. Gain = 230x.
Chopper on
Chopper off
Max input voltage range at C
S
+, C
S
34 mV – 44.5 mV. Gain = 65×.
26 mV – 34 mV. Gain = 85×.
20 mV – 26 mV. Gain = 110×.
16 mV – 20 mV. Gain = 135×.
12 mV – 16 mV. Gain = 175×.
9.5 mV – 12 mV. Gain = 230×
V
ZO
= 0
Reg 06h[7:1]. See Table 15.
SHRS = SHRO = 1 V
7 bits, 127 steps I
SHARE
slope
0 V ≤ V
CSCM
≤ 0.3 V. Gain = 65×.
V
CSCM
= input common mode.
V
CSCM
= 2.0 V, 0°C ≤ T
A
≤ 85°C.
Gain = 135×
V
CSCM
= 2.0 V, 0°C ≤ T
A
≤ 85°C.
Gain = 65×
See Figure 13.
Reg 17h[7] = 1. See Table 32.
Reg 17h[5] = 1. See Table 32.
0 ≤ V
TRIM
≤ 1.25 V
8 bits, 255 steps, V
CT
= 1.0 V
Reg 05h[7:0]. See Table 14.
Reg 17h[7] = 1. See Table 32.
Reg 06h = FEh. See Table 15.
Reg 17h[5] = 0, V
SHARE
= 2 V.
See Table 31
Reg 17h[5] = 1. See Table 32.
Reg 15h = 05h, approx 1 μA.
See Table 30. V
SHARE
= 2 V.
Gain setting = 4.5
Gain setting = 2.57
See Current-Transformer Input
Section.
15 steps Reg 15h[3:0]. See Table 30.
See Figure 38 and the Absolute
Maximum Ratings section.
5
±3
±6
65
85
110
135
175
230
2.0
65 to 99
0.4
8
+5
%
%
V/V
V/V
V/V
V/V
V/V
V/V
V
%
%
mV
%
Gain Accuracy
2, 4
, 20 mV at C
S
+, C
S
5
±1
+5
%
Gain Accuracy
2, 4
, 40 mV at C
S
+, C
S
–
2.5
±0.5
+2.5
%
SHARE BUS OFFSET
Current Share Offset Range
1.25
V
Zero Current Offset Trim Step
CURRENT TRANSFORMER SENSE INPUT, I
CT
0.4
5.5
%
mV
Gain Setting 0
4.5
V/V
Gain Setting 1
2.57
V/V
CT Input Sensitivity
CT Input Sensitivity
Input Impedance
2
Source Current
0.45
0.79
20
0.5
1.0
50
2.0
0.68
1.20
V
V
kΩ
μA
Source Current Step Size
Reverse Current for Extended SMBus
Addressing (Source Current)
5
3.5
170
5
7
nA
mA
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