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參數(shù)資料
| 型號： | ADM1487EARZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX HALF DUP RS485/422 8SOIC |
| 標準包裝： | 1,000 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | RS422，RS485 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
ADM485E/ADM487E/ADM1487E
Rev. B | Page 4 of 16
TIMING SPECIFICATIONS
VCC = 5 V ± 10%, TA = TMIN to TMAX, unless otherwise noted.
Table 3. ADM485E/ADM1487E
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DRIVER
Driver Propagation Delay Input to Output, Low to High
tDPLH
10
40
60
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see
Driver Propagation Delay Input to Output, High to Low
tDPHL
10
40
60
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see
Output Skew to Output
tSKEW
5
10
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see
Rise/Fall Time
tDR, tDF
3
20
40
ns
RDIFF = 54 Ω, CL1 = CL2 = 100 pF
(see
Enable Time to High Level
tDZH
45
70
ns
CL = 100 pF, S1 closed (see
Enable Time to Low Level
tDZL
45
70
ns
CL = 100 pF, S1 closed (see
Disable Time from Low Level
tDLZ
45
70
ns
CL = 15 pF, S1 closed (see
Disable Time from High Level
tDHZ
45
70
ns
CL = 15 pF, S1 closed (see
RECEIVER
Receiver Propagation Delay Input to Output, Low to High
tRPLH
20
60
200
ns
See
Receiver Propagation Delay Input to Output, High to Low
tRPHL
20
60
200
ns
See
|tPLH tPHL| Differential Receiver Skew
tSKEW
5
ns
See
Enable Time to Low Level
tRZL
25
50
ns
CL = 15 pF, S2 closed (see
Enable Time to High Level
tRZH
20
50
ns
CL = 15 pF, S1 closed (see
Disable Time from Low Level
tRLZ
20
50
ns
CL = 15 pF, S2 closed (see
Disable Time from High Level
tRHZ
20
50
ns
tPLH, tPHL < 50% of data period
MAXIMUM DATA RATE
fMAX
2.5
Mbps
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