參數(shù)資料
型號: ADM2486BRW
廠商: ANALOG DEVICES INC
元件分類: Buffer和線驅動
英文描述: IC QUAD OPTO-ISOLATOR ILQ2
中文描述: LINE TRANSCEIVER, PDSO16
封裝: MS013AA, SOIC-16
文件頁數(shù): 16/20頁
文件大?。?/td> 554K
代理商: ADM2486BRW
ADM2486
Rev. D | Page 5 of 20
TIMING SPECIFICATIONS
2.7 V ≤ VDD1 ≤ 5.5 V, 4.75 V ≤ VDD2 ≤ 5.25 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DRIVER
Maximum Data Rate
20
Mbps
Propagation Delay, tPLH, tPHL
25
45
55
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 7
RTS-to-DE Propagation Delay
20
35
55
ns
Pulse Width Distortion, tPWD
5
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 7 and Figure 12
Switching Skew, tSKEW
2
5
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 7 and Figure 12
Rise/Fall Time, tR, tF
5
15
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 7 and Figure 12
Enable Time
43
53
ns
Disable Time
43
55
ns
Enable Skew, |tAZH tBZL|, |tAZL tBZH|
1
3
ns
Disable Skew, |tAHZ tBLZ|, |tALZ tBHZ|
2
5
ns
RECEIVER
Propagation Delay, tPLH, tPHL
25
45
55
ns
CL = 15 pF, see Figure 10 and Figure 13
Differential Skew, tSKEW
5
ns
CL = 15 pF, see Figure 10 and Figure 13
Enable Time
3
13
ns
RL = 1 kΩ, CL = 15 pF, see Figure 11 and Figure 15
Disable Time
3
13
ns
RL = 1 kΩ, CL = 15 pF, see Figure 11 and Figure 15
POWER_VALID INPUT
Enable Time
1
2
μs
Disable Time
3
5
μs
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