參數(shù)資料
型號: ADM2486BRW
廠商: Analog Devices Inc
文件頁數(shù): 8/20頁
文件大小: 0K
描述: IC TXRX RS-485 ISOLATED 16-SOIC
標準包裝: 47
系列: iCoupler®
類型: 收發(fā)器,隔離式
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: RS422/RS485
電源電壓: 3V,5V
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC
包裝: 管件
其它名稱: Q1893052
ADM2486
Data Sheet
Rev. E | Page 16 of 20
APPLICATIONS INFORMATION
PC BOARD LAYOUT
The ADM2486 isolated RS-485 transceiver requires no external
interface circuitry for the logic interfaces. Power supply bypassing
is strongly recommended at the input and output supply pins
(see Figure 29). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16
for VDD2. The capacitor value should be between 0.01 F and 0.1 F.
The total lead length between both ends of the capacitor and the
input power supply pin should not exceed 20 mm. Bypassing
between Pin 1 and Pin 8 and between Pin 9 and Pin 16 should
also be considered unless the ground pair on each package side
is connected close to the package.
VDD1
GND1
RxD
RE
RTS
TxD
PV
GND1
VDD2
GND2
NC
B
A
NC
DE
GND2
04604-
002
NC = NO CONNECT
ADM2486
Figure 29. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care
should be taken to ensure that board coupling across the isola-
tion barrier is minimized. Furthermore, the board layout should
be designed such that any coupling that does occur equally affects
all pins on a given component side. Failure to ensure this could
cause voltage differentials between pins exceeding the device’s
Absolute Maximum Ratings, thereby leading to latch-up or
permanent damage.
POWER_VALID INPUT
To avoid chatter on the A and B outputs caused by slow power-
up and power-down transients on VDD1 (>100 s/V), the device
features a power_valid (PV) digital input. This pin should be
driven low until VDD1 exceeds 2.0 V. When VDD1 is greater than
2.0 V, this pin should be driven high. Conversely, upon power-
down, PV should be driven low before VDD1 reaches 2.0 V (see
If the PV pin is driven with an open-drain output, the
recommended value for the pull-up resistor is a 10 k resistor,
bypassed with a 100 pF capacitor to GND1 (see Figure 31).
The power_valid input can be driven, for example, by the
output of a system reset circuit, such as the ADM809Z, which
has a threshold voltage of 2.32 V.
ADM809Z
ADM2486
VDD1
PV
GND1
VDD1
RESET
VDD1
tPOR
2.32V
2.0V
2.32V
2.0V
04604-
023
Figure 30. Driving PV with ADM809Z
ADM809Z
ADM2486
VDD1
PV
GND1
VDD1
RESET
VDD1
tPOR
2.32V
2.0V
2.32V
2.0V
04604-
030
100pF
10k
Figure 31. Driving PV with an Open-Drain Output
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