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參數(shù)資料
| 型號(hào)： | ADM3232EARNZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/12頁 |
| 文件大小： | 0K |
| 描述： | IC RCVR/LINEDRIVER RS232 16-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Power Line Monitoring |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 2/2 |
| 規(guī)程： | RS232 |
| 電源電壓： | 3 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
ADM3232E
Rev. B | Page 8 of 12
THEORY OF OPERATION
The ADM3232E is a single-channel RS-232 line driver/receiver.
Step-up voltage converters, coupled with level-shifting transmitters
and receivers, allow RS-232 levels to be developed while operating
from a single 3.3 V supply.
CMOS technology is used to keep the power dissipation to an
absolute minimum, allowing maximum battery life in portable
applications.
CIRCUIT DESCRIPTION
The internal circuitry consists of the following main sections:
A charge pump voltage converter
A 3.3 V logic to RS-232 transmitter
An RS-232 to 3.3 V logic receiver
Charge Pump Voltage Converter
The charge pump voltage converter consists of a 200 kHz
oscillator and a switching matrix. The converter generates a
±6.6 V supply from the input 3.3 V level. This is accomplished
in two stages by using a switched capacitor technique as shown
in Figure 10. First, the 3.3 V input supply is doubled to 6.6 V by
using Capacitor C1 as the charge storage element. The +6.6 V
level is then inverted to generate 6.6 V, using C2 as the storage
element.
Capacitor C3 and Capacitor C4 are used to reduce the output
ripple. Their values are not critical and can be increased, if desired.
Capacitor C3 is shown connected between V+ and VCC. It is also
acceptable to connect this capacitor between V+ and GND.
If desired, larger capacitors (up to 10 μF) can be used for
Capacitor C1 to Capacitor C4.
C1+
C2+
C1–
C2–
VCC
V–
V+
T1IN
T1OUT
T2IN
T2OUT
R1OUT
R1IN
R2OUT
R2IN
TTL/CMOS
INPUTS
RS-232
OUTPUTS
TTL/CMOS
OUTPUTS
RS-232
INPUTS*
T1
T2
R1
R2
+
C1
0.1F
10V
C2
0.1F
10V
GND
ADM3232E
C3
0.1F
6.3V
+3.3V INPUT
+3.3V TO +6.6V
VOLTAGE
DOUBLER
+6.6V TO –6.6V
VOLTAGE
INVERTER
C5
0.1F
+
C4
0.1F
10V
+
*INTERNAL 5k PULL-DOWN RESISTOR
ON EACH RS-232 INPUT.
5k
06
41
0-
0
1
0
Figure 10. Typical Operating Circuit
C1
+
C3
+
S3
S4
S1
S2
INTERNAL
OSCILLATOR
VCC
GND
VCC
V+ = 2VCC
06
41
0-
0
11
Figure 11. Charge Pump Voltage Doubler
C2
+
C4
+
S3
S4
S1
S2
INTERNAL
OSCILLATOR
V+
GND
V– = –(V+)
GND
FROM
VOLTAGE
DOUBLER
06
41
0-
0
12
Figure 12. Charge Pump Voltage Inverter
3.3 V Logic to RS-232 Transmitter
The drivers convert 3.3 V logic input levels into RS-232 output
levels. With VCC = 3.3 V and driving an RS-232 load, the output
voltage swing is typically ±6 V.
RS-232 to 3.3 V Logic Receiver
The receivers are inverting level shifters that accept RS-232 input
levels and translate them into 3 V logic output levels. The inputs
have internal 5 kΩ pull-down resistors to ground and are
pro-
tected against overvoltages up to ±30 V. Unconnected inputs
are pulled to 0 V by the internal 5 kΩ pull-down resistor. This
results in a Logic 1 output level for unconnected inputs or for
inputs connected to GND.
The receivers have Schmitt trigger inputs with a hysteresis level
of 0.4 V. This ensures error-free reception for both noisy inputs
and for inputs with slow transition times.
ESD Protection on RS-232 Pins
All RS-232 (TxOUT and RxIN) inputs and outputs are protected
against electrostatic discharges (up to ±15 kV). This ensures
compliance with IEC 1000-4-2 requirements.
HIGH BAUD RATE
The ADM3232E features high slew rates, permitting data trans-
mission at rates well in excess of the EIA-232E specifications.
RS-232 voltage levels are maintained at data rates up to 460 kbps,
even under worst-case loading conditions. The slew rate is
internally controlled to less than 30 V/μs to minimize EMI
interference.
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| ADM3232EARUZ | 制造商:Analog Devices 功能描述:IC, RS-232 TXRX, 460KBPS, 5.5V, TSSOP-16 |
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