ADM483E
Rev. A | Page 9 of 16
TEST CIRCUITS AND SWITCHING CHARACTERISTICS
Z
Y
VOD
VOC
RL
0
60
12
-01
5
Figure 15. Driver DC Test Load
DI
DE
5V
A
B
RL
CL
VOD
06
01
2
-01
6
Figure 16. Driver Timing Test Circuit
5V
1.5V
1/2VO
10%
90%
10%
DI
A
B
0V
+VO
VO
–VO
VDIFF
tSKEW = tDPLH – tDPHL
VDIFF = V (A) – V (B)
tDR
tDPLH
tDPHL
tDF
1/2 VO
06
01
2-
01
7
Figure 17. Driver Propagation Delays
GENERATOR
0 OR 5V
50
RL = 500
OUT
CL
S1
1.5V
5V
0V
VOH
0V
0.5V
2.3V
OUT
DE
tDHZ
tDZH,
tDZH(SHDN)
D
0
601
2-
0
18
Figure 18. Driver Enable and Disable Times (tDHZ, tDZH, tDZH(SHDN))
GENERATOR
0V OR 5V
50
D
RL = 500
VCC
OUT
CL
S1
VCC/2
5V
0V
0.5V
2.3V
VOL
OUT
VCC
DE
tDLZ
tDZL,
tDZL(SHDN)
0
60
12
-01
9
Figure 19. Driver Enable and Disable Times (tDZL, tDLZ, tDZL(SHDN))
ATE
B
RECEIVER
OUTPUT
A
R
VID
060
12
-02
0
Figure 20. Receiver Propagation Delay Test Circuit
THE RISE TIME AND FALL TIME OF INPUT A AND INPUT B < 4ns
+1V
–1V
tRPHL
tRPLH
1.5V
B
RO
VOH
VOL
A
0
60
12-
021
Figure 21. Receiver Propagation Delays