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參數(shù)資料
型號: ADM4850ACPZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 11/16頁
文件大?。?/td> 0K
描述: IC TXRX RS485/422 115KBPS 8LFCSP
標準包裝: 1
類型: 收發(fā)器
驅動器/接收器數(shù): 1/1
規(guī)程: RS422,RS485
電源電壓: 4.75 V ~ 5.25 V
安裝類型: 表面貼裝
封裝/外殼: 8-VFDFN 裸露焊盤,CSP
供應商設備封裝: 8-LFCSP-VD(3x3)
包裝: 標準包裝
其它名稱: ADM4850ACPZ-REEL7DKR
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
Rev. D | Page 4 of 16
ADM4850/ADM4854 TIMING SPECIFICATIONS
VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DRIVER
Maximum Data Rate
115
kbps
Propagation Delay, tPLH, tPHL
600
2500
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
Skew, tSKEW
70
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
Rise/Fall Times, tR, tF
600
2400
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
Enable Time, tZH
2000
ns
RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4850
Disable Time, tZL
2000
ns
RL = 500 Ω, CL = 15 pF, see Figure 21, ADM4850
Enable Time from Shutdown
4000
ns
RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4850
RECEIVER
Propagation Delay, tPLH, tPHL
400
1000
ns
CL = 15 pF, see Figure 22
Differential Skew, tSKEW
255
ns
CL = 15 pF, see Figure 22
Enable Time
5
50
ns
RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4850
Disable Time
20
50
ns
RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4850
Enable Time from Shutdown
4000
ns
RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4850
Time to Shutdown
50
330
3000
ns
1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4851/ADM4855 TIMING SPECIFICATIONS
VCC = 5 V ± 5%, TA = TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DRIVER
Maximum Data Rate
500
kbps
Propagation Delay, tPLH, tPHL
250
600
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
Skew, tSKEW
40
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
Rise/Fall Times, tR, tF
200
600
ns
RLDIFF = 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
Enable Time, tZH
1000
ns
RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4851
Disable Time, tZL
1000
ns
RL = 500 Ω, CL = 15 pF, see Figure 21, ADM4851
Enable Time from Shutdown
4000
ns
RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4851
RECEIVER
Propagation Delay, tPLH, tPHL
400
1000
ns
CL = 15 pF, see Figure 22
Differential Skew, tSKEW
250
ns
CL = 15 pF, see Figure 22
Enable Time
5
50
ns
RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4851
Disable Time
20
50
ns
RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4851
Enable Time from Shutdown
4000
ns
RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4851
Time to Shutdown
50
330
3000
ns
1 The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
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