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參數(shù)資料
| 型號： | ADMC326YR-XXX-YY |
| 英文描述： | MOTOR CONTROLLER |
| 中文描述： | 電機(jī)控制器 |
| 文件頁數(shù)： | 18/32頁 |
| 文件大小： | 237K |
| 代理商： | ADMC326YR-XXX-YY |
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ADMC326
–18–
REV. C
V
REF
3.5V
0.3V
MINIMUM
RAMP
TARGET
RAMP
Figure 15. Current Ramp
ADC Registers
The configuration of all registers of the ADC System is shown
at the end of the data sheet.
AUXILIARY PWM TIMERS
Overview
The ADMC326 provides two variable frequency, variable duty
cycle, 8-bit, auxiliary PWM outputs that are available at the
AUX1 and AUX0 pins when enabled. These auxiliary PWM
outputs can be used to provide switching signals to other cir-
cuits in a typical motor control system such as power factor
corrected front-end converters or other switching power con-
verters. Alternatively, by addition of a suitable filter network,
the auxiliary PWM output signals can be used as simple single-
bit digital-to-analog converters.
The auxiliary PWM system of the ADMC326 can operate in
two different modes: independent mode, or offset mode. The
operating mode of the auxiliary PWM system is controlled by Bit 8
of the MODECTRL register. Setting Bit 8 of the MODECTRL
register places the auxiliary PWM system in the independent
mode. In this mode, the two auxiliary PWM generators are
completely independent and separate switching frequencies and
duty cycles may be programmed for each auxiliary PWM output.
In this mode, the 8-bit AUXTM0 register sets the switching fre-
quency of the signal at the AUX0 output pin. Similarly, the
8-bit AUXTM1 register sets the switching frequency of the sig-
nal at the AUX1 pin. The fundamental time increment for the
auxiliary PWM outputs is twice the DSP instruction rate (or
2 t
CK
) and the corresponding switching periods are given by:
T
AUX
0
=
2
×
(
AUXTM
0 + 1)
×
t
CK
T
AUX
1
=
2
×
(
AUXTM
1
+
1)
×
t
CK
Since the values in both
AUXTM
0 and
AUXTM
1 can range
from 0 to 0xFF, the achievable switching frequency of the auxil-
iary PWM signals may range from 39.1 kHz to 10 MHz for a
CLKOUT frequency of 20 MHz.
The on-time of the two auxiliary PWM signals is programmed
by the two 8-bit AUXCH0 and AUXCH1 registers, according to:
T
ON
,
AUX
0
= 2
×
(
AUXCH
0)
×
t
CK
T
ON
,
AUX
1
= 2
×
(
AUXCH
1)
×
t
CK
so that output duty cycles from 0% to 100% are possible. Duty
cycles of 100% are produced if the on-time value exceeds the
period value. Typical auxiliary PWM waveforms in independent
mode are shown in Figure 16(a).
When Bit 8 of the MODECTRL register is cleared, the auxiliary
PWM channels are placed in offset mode. In offset mode, the
switching frequency of the two signals on the AUX0 and AUX1
pins are identical and controlled by AUXTM0 in a manner
similar to that previously described for independent mode. In
addition, the on times of both the AUX0 and AUX1 signals are
controlled by the AUXCH0 and AUXCH1 registers as before.
However, in this mode the AUXTM1 register defines the offset
time from the rising edge of the signal on the AUX0 pin to that
on the AUX1 pin according to:
T
OFFSET
= 2
×
(
AUXTM
1 + 1)
×
t
CK
For correct operation in this mode, the value written to the
AUXTM
1 register must be less than the value written to the
AUXTM
0 register. Typical auxiliary PWM waveforms in offset
mode are shown in Figure 16(b). Again, duty cycles from 0% to
100% are possible in this mode.
In both operating modes, the resolution of the auxiliary PWM
system is eight bits only at the minimum switching frequency
(AUXTM0 = AUXTM1 = 255 in independent mode, AUXTM0
= 255 in offset mode). Obviously, as the switching frequency is
increased, the resolution is reduced.
Values can be written to the auxiliary PWM registers at any time.
However, new duty cycle values written to the AUXCH0 and
AUXCH1 registers only become effective at the start of the next
cycle. Writing to the AUXTM0 or AUXTM1 registers causes the
internal timers to be reset to 0 and new PWM cycles to begin.
By default following a reset, Bit 8 of the MODECTRL register
is cleared, thus enabling offset mode. In addition, the registers
AUXTM0 and AUXTM1 default to 0xFF, corresponding to the
minimum switching frequency and zero offset. The on-time reg-
isters AUXCH0 and AUXCH1 default to 0x00.
Auxiliary PWM Interface, Registers and Pins
The registers of the auxiliary PWM system are summarized at
the end of the data sheet.
AUX0
AUX1
2 (AUXTM0 + 1)
2 (AUXTM1 + 1)
2 AUXCH1
2 AUXCH1
2 AUXCH0
(a) Independent Mode
AUX0
AUX1
2 (AUXTM1 + 1)
2 (AUXTM0 + 1)
2 AUXCH0
2 (AUXTM0 + 1)
2 AUXCH1
(b) Offset Mode
Figure 16. Typical Auxiliary PWM Signals.
(All Times in Increments of t
CK
)
相關(guān)PDF資料 |
PDF描述 |
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| ADMC340BST | Controller Miscellaneous - Datasheet Reference |
| ADMC340VST-XXX-XXXX | Controller Miscellaneous - Datasheet Reference |
| ADMC341YR-XXX-XXXX | Controller Miscellaneous - Datasheet Reference |
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相關(guān)代理商/技術(shù)參數(shù) |
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| ADMC328TR | 制造商:AD 制造商全稱:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller with Current Sense |
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