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| 型號： | ADMP521ACEZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MEMS MICROPHONE ULTRA LN 5LGA |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | ADMP521 |
| 類型： | MEMS（硅） |
| 輸出類型： | 數(shù)字 |
| 方向： | 全向 |
| 頻率范圍： | 100Hz ~ 16kHz |
| 靈敏度： | -26dB ±3dB |
| 信噪比： | 65dB |
| 電壓 - 額定： | 1.8 ~ 3.3V |
| 電流 - 電源： | 1.2mA |
| 端口位置： | 底部 |
| 密封等級： | 無 |
| 端子： | 焊盤 |
| 尺寸/尺寸： | 0.157" L x 0.118" W（4.00mm x 3.00mm） |
| 高度（最大）： | 0.043"（1.10mm） |
| 形狀： | 矩形 |
| 包裝： | 帶卷 (TR) |
ADMP521
Data Sheet
Rev. A | Page 8 of 16
THEORY OF OPERATION
PDM DATA FORMAT
The output from the DATA pin of the ADMP521 is in PDM
format. This data is the 1-bit output of a fourth-order Σ-Δ
modulator. The data is encoded so that the left channel is clocked
on the falling edge of CLK and the right channel is clocked on
the rising edge of CLK. After driving the DATA signal high or
low in the appropriate half frame of the CLK signal, the DATA
driver of the microphone tristates. In this way, two microphones,
one set to the left channel and the other to right, can drive a
single DATA line. See Figure 3 for a timing diagram of the PDM
data format; the DATA1 and DATA2 lines shown in this figure are
two halves of the single physical DATA signal. Figure 10 shows a
diagram of the two stereo channels sharing a common DATA line.
If only one microphone is connected to the DATA signal, the
output is only clocked on a single edge (see Figure 9). For example,
a left channel microphone is never clocked on the rising edge of
CLK. In a single microphone application, each bit of the DATA
signal is typically held for the full CLK period until the next
transition because the leakage of the DATA line is not enough
to discharge the line while the driver is tristated.
See Table 6 for the channel assignments according to the logic
level on the L/R SELECT pin.
Table 6. ADMP521 Channel Setting
L/R SELECT Setting
Channel
Low (tie to ground)
DATA1 (right)
High (tie to VDD)
DATA2 (left)
For PDM data, the density of the pulses indicates the signal
amplitude. A high density of high pulses indicates a signal near
positive full scale and a high density of low pulses indicates a signal
near negative full scale. A perfect zero (dc) audio signal shows
an alternating pattern of high and low pulses.
The output PDM data signal has a small dc offset of between 3% to
7% of full scale. This dc signal is typically removed by a high-pass
filter in the codec that is connected to the digital microphone.
DATA1 (R)
CLK
DATA
10141-
012
Figure 9. Mono PDM Format
DATA2 (L)
DATA1 (R)
CLK
DATA
10141-
013
Figure 10. Stereo PDM Format
PDM MICROPHONE SENSITIVITY
The acoustic input levels of the microphone in dB SPL are rms
measurements; however, the sensitivity and output level of a
digital microphone is given as a peak level. This is because its
output is referenced to the full-scale digital word, which is a
peak value. This convention is different from the output levels
of analog microphones, which are given as an rms voltage. The
ADMP521 has a sensitivity of 26 dBFS. A 94 dB SPL (rms) input
signal gives a 26 dBFS peak output level; therefore, the rms
level of this digital output is 29 dBFS.
This convention of using peak levels to specify the output of
digital microphones must be kept in mind when configuring
downstream signal processing that may rely on precise signal
levels. For example, dynamic range processors (compressors,
limiters, noise gates) typically set thresholds based on rms
signal levels; therefore, adjust the signals of the microphone
from peak to rms by lowering the dBFS value by 3 dB.
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