- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378286 > ADN2525 (Analog Devices, Inc.) 10.7 Gbps Active Back-Termination, Differential Laser Diode Driver PDF資料下載
參數(shù)資料
| 型號： | ADN2525 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10.7 Gbps Active Back-Termination, Differential Laser Diode Driver |
| 中文描述： | 10.7 Gbps的主動背終止，差分激光二極管驅(qū)動器 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 531K |
| 代理商： | ADN2525 |
ADN2525
DESIGN EXAMPLE
This design example covers
Rev. 0 | Page 14 of 16
Headroom calculations for IBIAS, IMODP, and IMODN pins.
Calculation of the typical voltage required at the BSET and
MSET pins in order to produce the desired bias and
modulation currents.
This design example assumes that the resistance of the TOSA is
25 , the forward voltage of the laser at low current is V
F
= 1 V,
IBIAS = 40 mA, IMOD = 60 mA, and VCC = 3.3 V.
Headroom Calculations
To ensure proper device operation, the voltages on the IBIAS,
IMODP, and IMODN pins must meet the compliance voltage
specifications in Table 1.
Considering the typical application circuit shown in Figure 33,
the voltage at the IBIAS pin can be written as
V
IBIAS
= VCC V
F
(IBIAS × R
TOSA
) V
LA
where:
VCC
is the supply voltage.
V
F
is the forward voltage across the laser at low current.
R
TOSA
is the resistance of the TOSA.
V
LA
is the dc voltage drop across L5, L6, L7, and L8.
V
LB
is the dc voltage drop across L1, L2, L3, and L4.
For proper operation, the minimum voltage at the IBIAS pin
should be greater than 0.6 V, as specified by the minimum
IBIAS compliance specification in Table 1.
Assuming that the voltage drop across the 25 transmission
lines is negligible and that V
LA
=0 V, V
F
= 1 V, IBIAS = 40 mA,
V
IBIAS
= 3.3 1 (0.04
×
25) = 1.3 V
V
IBIAS
= 1.3 V > 0.6 V, which satisfies the requirement.
The maximum voltage at the IBIAS pin must be less than the
maximum IBIAS compliance specification as described by the
following equation:
V
COMPLIANCE_MAX
=
VCC
0.75 4.4 ×
IBIAS
(A)
For this example:
V
COMPLIANCE_MAX
=
VCC – 0.75 4.4 × 0.04 = 2.53 V
V
IBIAS
= 1.3 V < 2.53 V, which satisfies the requirement.
To calculate the headroom at the modulation current pins
(IMODP, IMODN), the voltage has a dc component equal to
VCC due to the ac-coupled configuration and a swing equal to
IMOD
×
25 . For proper operation of the ADN2525, the
voltage at each modulation output pin should be within the
normal operation region shown in Figure 30.
Assuming V
LB
= 0 V and IMOD = 60 mA, the minimum voltage
at the modulation output pins is equal to
VCC
(
IMOD
× 25)/2 =
VCC
0.75
VCC
0.75 >
VCC
1.1 V, which satisfies the requirement.
The maximum voltage at the modulation output pins is equal to
VCC
+ (
IMOD
× 25)/2 =
VCC
+ 0.75
VCC
+ 0.75 <
VCC
+ 1.1 V, which satisfies the requirement.
Headroom calculations must be repeated for the minimum and
maximum values of the required IBIAS and IMOD ranges to
ensure proper device operation over all operating conditions.
BSET and MSET Pin Voltage Calculation
To set the desired bias and modulation currents, the BSET and
MSET pins of the ADN2525 must be driven with the appropriate
dc voltage. The voltage range required at the BSET pin to generate
the required IBIAS range can be calculated using the BSET
voltage to IBIAS gain specified in Table 1. Assuming that IBIAS
= 40 mA and the typical IBIAS/V
BSET
ratio of 100 mA/V, the
BSET voltage is given by
V
4
=
100
40
mA/V
100
(mA)
=
=
IBIAS
V
BSET
The BSET voltage range can be calculated using the required
IBIAS range and the minimum and maximum BSET voltage to
IBIAS gain values specified in Table 1.
The voltage required at the MSET pin to produce the desired
modulation current can be calculated using
K
IMOD
V
MSET
=
where
K
is the
MSET
voltage to
IMOD
ratio.
The value of K depends on the actual resistance of the TOSA.
It can be read using the plot shown in Figure 29. For a TOSA
resistance of 25 , the typical value of K = 120 mA/V. Assuming
that IMOD = 60 mA and using the preceding equation, the
MSET voltage is given by
V
5
=
120
60
mA/V
120
(mA)
=
=
IMOD
V
MSET
The MSET voltage range can be calculated using the required
IMOD range and the minimum and maximum K values. These
can be obtained from the minimum and maximum curves in
Figure 29.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADN2525ACPZ-R2 | 10.7 Gbps Active Back-Termination, Differential Laser Diode Driver |
| ADN2525ACPZ-REEL7 | 10.7 Gbps Active Back-Termination, Differential Laser Diode Driver |
| ADN2525ACPZ-WP | 10.7 Gbps Active Back-Termination, Differential Laser Diode Driver |
| ADP3415 | Dual MOSFET Driver with Bootstrapping |
| ADP3415LRM-REEL | Dual MOSFET Driver with Bootstrapping |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADN2525ACPZ-500R7 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| ADN2525ACPZ-500RL7 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| ADN2525ACPZ-R2 | 功能描述:IC LASER DRIVER 10.7GBPS 16LFCSP RoHS:是 類別:集成電路 (IC) >> PMIC - 激光驅(qū)動器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:60 系列:- 類型:激光二極管驅(qū)動器 數(shù)據(jù)速率:- 通道數(shù):4 電源電壓:3.3V 電流 - 電源:- 電流 - 調(diào)制:- 電流 - 偏置:- 工作溫度:0°C ~ 70°C 封裝/外殼:40-TQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN EP 包裝:托盤 安裝類型:表面貼裝 |
| ADN2525ACPZ-REEL7 | 功能描述:IC LASER DRIVER 10.7GBPS 16LFCSP RoHS:是 類別:集成電路 (IC) >> PMIC - 激光驅(qū)動器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:60 系列:- 類型:激光二極管驅(qū)動器 數(shù)據(jù)速率:- 通道數(shù):4 電源電壓:3.3V 電流 - 電源:- 電流 - 調(diào)制:- 電流 - 偏置:- 工作溫度:0°C ~ 70°C 封裝/外殼:40-TQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN EP 包裝:托盤 安裝類型:表面貼裝 |
| ADN2525ACPZ-WP | 制造商:Analog Devices 功能描述:Laser Driver 10.7Gbps 1-CH 16-Pin LFCSP EP Waffle 制造商:Analog Devices 功能描述:LASER DRVR 10.7GBPS 1CH 16LFCSP - Waffle Pack |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。