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參數(shù)資料
| 型號： | ADN2525ACPZ-R2 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 其它接口 |
| 英文描述： | 10.7 Gbps Active Back-Termination, Differential Laser Diode Driver |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, QCC16 |
| 封裝： | 3 X 3 MM, LEAD FREE, MO-220VEED-2, LFCSP-16 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 531K |
| 代理商： | ADN2525ACPZ-R2 |
ADN2525
SPECIFICATIONS
VCC = VCC
MIN
to VCC
MAX
, T
A
= 40°C to +85°C, 50 differential load resistance, unless otherwise noted.
Typical values are specified at 25°C, IMOD = 40 mA.
Table 1.
Parameter
Min
Typ
BIAS CURRENT (IBIAS)
Bias Current Range
10
Bias Current while ALS Asserted
Compliance Voltage
1
0.6
0.6
MODULATION CURRENT (IMODP, IMODN)
Modulation Current Range
10
Modulation Current while ALS Asserted
Rise Time (20% to 80%)
2, 3
24
Fall Time (20% to 80%)
2
,
24
Random Jitter
2
,
0.4
Deterministic Jitter
3,
4
7.2
Differential |S
22
|
10
14
Compliance Voltage
1
VCC 1.1
DATA INPUTS (DATAP, DATAN)
Input Data Rate
Differential Input Swing
0.4
Differential |S
11
|
16.8
Input Termination Resistance
85
100
BIAS CONTROL INPUT (BSET)
BSET Voltage to IBIAS Gain
75
100
BSET Input Resistance
800
1000
MODULATION CONTROL INPUT (MSET)
MSET Voltage to IMOD Gain
70
88
MSET Input Resistance
800
1000
BIAS MONITOR (IBMON)
IBMON to IBIAS Ratio
10
Accuracy of IBIAS to IBMON Ratio
5.0
4.0
2.5
2
AUTOMATIC LASER SHUTDOWN (ALS)
V
IH
2.4
V
IL
I
IL
20
I
IH
0
ALS Assert Time
Rev. 0 | Page 3 of 16
Max
100
100
VCC – 1.2
VCC – 0.8
80
0.5
32.5
32.5
0.9
12
VCC + 1.1
10.7
1.6
115
120
1200
110
1200
+5.0
+4.0
+2.5
+2
0.8
+20
200
10
Unit
mA
μA
V
V
mA diff
mA diff
ps
ps
ps rms
ps p-p
dB
dB
V
Gbps
V p-p diff
dB
mA/V
mA/V
μA/mA
%
%
%
%
V
V
μA
μA
μs
Test Conditions/Comments
ALS = high
IBIAS = 100 mA
IBIAS = 10 mA
R
LOAD
= 5 to 50 differential
ALS = high
5 GHz < F < 10 GHz, Z
0
= 50 differential
F < 5 GHz, Z
0
= 50 differential
NRZ
Differential ac-coupled
F < 10 GHz, Z
0
= 100 differential
Differential
See Figure 29
10 mA
≤
IBIAS < 20 mA, R
IBMON
= 1 k
20 mA
≤
IBIAS < 40 mA, R
IBMON
= 1 k
40 mA
≤
IBIAS < 70 mA, R
IBMON
= 1 k
70 mA
≤
IBIAS < 100 mA, R
IBMON
= 1 k
Rising edge of ALS to fall of IBIAS and IMOD below
10% of nominal; see Figure 2
Falling edge of ALS to rise of IBIAS and IMOD above
90% of nominal; see Figure 2
V
BSET
= V
MSET
= 0 V
V
BSET
= V
MSET
= 0 V. I
SUPPLY
= I
CC
+ IMODP + IMODN
3
3
ALS Negate Time
10
μs
POWER SUPPLY
V
CC
I
CC5
I
SUPPLY6
3.07
3.3
39
157
3.53
45
176
V
mA
mA
1
Refers to the voltage between the pin for which the compliance voltage is specified and GND.
2
The pattern used is composed by a repetitive sequence of eight 1s followed by eight 0s at 10.7 Gbps.
3
Measured using the high speed characterization circuit shown in Figure 3.
4
The pattern used is K28.5 (00111110101100000101) at 10.7 Gbps rate.
5
Only includes current in the ADN2525 VCC pins.
6
Includes current in ADN2525 VCC pins and dc current in IMODP and IMODN pull-up inductors. See the
section for total supply current calculation.
Power Consumption
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