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參數(shù)資料
| 型號： | ADN2815ACPZ-500RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/24頁 |
| 文件大小： | 0K |
| 描述： | IC CLK/DATA REC 1.25GBPS 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH |
| 輸入： | CML |
| 輸出： | LVDS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.25GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ（5x5） |
| 包裝： | 帶卷 (TR) |
ADN2815
Data Sheet
Rev. C | Page 16 of 24
Stop and start conditions can be detected at any stage of the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an
immediate jump to the idle condition. During a given SCK high
period, the user should issue one start condition, one stop
condition, or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADN2815 does not issue an acknowledge and returns to the idle
condition. If the user exceeds the highest subaddress while
reading back in autoincrement mode, then the highest subad-
dress register contents continue to be output until the master
device issues a no-acknowledge. This indicates the end of a
read. In a no-acknowledge condition, the SDATA line is not
pulled low on the ninth pulse. See Figure 7 and Figure 8 for
sample read and write data transfers and Figure 9 for a more
detailed timing diagram.
REFERENCE CLOCK (OPTIONAL)
A reference clock is not required to perform clock and data
recovery with the ADN2815. However, support for an optional
reference clock is provided. The reference clock can be driven
differentially or single-ended. If the reference clock is not being
used, then REFCLKP should be tied to VCC, and REFCLKN
can be left floating or tied to VEE (the inputs are internally
terminated to VCC/2). See Figure 16 through Figure 18 for
sample configurations.
The REFCLK input buffer accepts any differential signal with a
peak-to-peak differential amplitude of greater than 100 mV (for
example, LVPECL or LVDS) or a standard single-ended low
voltage TTL input, providing maximum system flexibility.
Phase noise and duty cycle of the reference clock are not critical
and 100 ppm accuracy is sufficient.
04952-
0-
021
100k
VCC/2
100k
ADN2815
REFCLKP
10
11
REFCLKN
BUFFER
Figure 16. Differential REFCLK Configuration
04952-
0-
022
100k
VCC/2
100k
ADN2815
REFCLKP
OUT
REFCLKN
BUFFER
VCC
CLK
OSC
Figure 17. Single-Ended REFCLK Configuration
04952-
0-
023
100k
VCC/2
100k
ADN2815
REFCLKP
10
11
NC
REFCLKN
BUFFER
VCC
Figure 18. No REFCLK Configuration
The two uses of the reference clock are mutually exclusive. The
reference clock can be used either as an acquisition aid for the
ADN2815 to lock onto data or to measure the frequency of the
incoming data to within 0.01%. (There is the capability to
measure the data rate to approximately ±10% without the use of
a reference clock.) The modes are mutually exclusive because, in
the first use, the user knows exactly what the data rate is and
wants to force the part to lock onto only that data rate; in the
second use, the user does not know what the data rate is and
wants to measure it.
Lock-to-reference mode is enabled by writing a 1 to I2C Register
Bit CTRLA[0]. Fine data rate readback mode is enabled by
writing a 1 to I2C Register Bit CTRLA[1]. Writing a 1 to both of
these bits at the same time causes an indeterminate state and is
not supported.
Using the Reference Clock to Lock onto Data
In this mode, the ADN2815 locks onto a frequency derived
from the reference clock according to
Data Rate/2CTRLA[5:2] = REFCLK/2CTRLA[7:6]
The user must know exactly what the data rate is and provide a
reference clock that is a function of this rate. The ADN2815 can
still be used as a continuous rate device in this configuration,
provided that the user has the ability to provide a reference
clock that has a variable frequency (see Application Note
AN-632).
The reference clock can be anywhere between 10 MHz and
160 MHz. By default, the ADN2815 expects a reference clock of
between 10 MHz and 20 MHz. If it is between 20 MHz and
40 MHz, 40 MHz and 80 MHz, or 80 MHz and 160 MHz, the
user needs to configure the ADN2815 to use the correct
reference frequency range by setting two bits of the CTRLA
register, CTRLA[7:6].
Table 11. CTRLA Settings
CTRLA[7:6]
Range (MHz)
CTRLA[5:2]
Ratio
00
10 to 20
0000
1
01
20 to 40
0001
2
10
40 to 80
n
2n
11
80 to 160
1000
256
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