參數(shù)資料
型號(hào)： ADN2850ACP250-RL7
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字電位計(jì)
英文描述： Nonvolatile Memory, Dual 1024 Position Programmable Resistors
中文描述： DUAL 250K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 1024 POSITIONS, QCC16
封裝： 5 X 5 MM, LFCSP-16
文件頁(yè)數(shù)： 3/18頁(yè)
文件大小： 270K
代理商： ADN2850ACP250-RL7
PRELIMINARY TECHNICAL DATA
Nonvolatile Memory Programmable Resistors
ADN2850
REV PrH, 13, AUG 2001
3
ELECTRICAL CHARACTERISTICS 25K , 250K OHM VERSIONS
(V
DD
= +3V to +5.5V and,
-40°C < T
A
< +85°C unless otherwise noted
.)
Parameter
Symbol
Conditions
Min
Typ
1
Max
Units
INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 4, 9)
Clock Cycle Time (t
CYC
)
CS
Setup Time
CLK Shutdown Time to
CS
rise
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CS
to SDO - SPI line acquire
CS
to SDO - SPI line release
CLK to SDO Propagation Delay
10
CLK to SDO Data Hold Time
CS
High Pulse Width
CS
High to
CS
High
RDY Rise to
CS
Fall
CS
Rise to RDY fall time
Read/Store to Nonvolatile EEMEM
11
CS
Rise to Clock Edge Setup
Preset Pulse Width (Asynchronous)
Preset Response Time to RDY High
t
1
t
2
t
3
t
4
, t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
PRW
t
PRESP
20
10
1
10
5
5
ns
ns
t
CYC
ns
ns
ns
ns
ns
ns
ns
ns
t
CYC
μ
s
ms
ms
ns
ns
us
Clock level high or low
FromPositive CLK transition
FromPositive CLK transition
6
34
34
40
100
100
R
P
= 2.2K
, C
L
< 20pF
R
P
= 2.2K
, C
L
< 20pF
0
10
4
0
1
0.11
Applies to Command 2
H
, 3
H
, 9
H
25
10
50
Not shown in timng diagram
PR
pulsed low to refreshed wiper positions
70
FLASH/EE MEMORY RELIABILITY
13
Endurance
Data Retention
14
100,000
Cycles
Years
100
NOTES:
1.
2.
Typicals represent average readings at +25°C and V
DD
= +5V.
Resistor position nonlinearity error R-INL is the deviation froman ideal value measured between the maximumresistance and the mnimumresistance wiper positions. R-DNL measures the
relative step change fromideal between successive tap positions. I
W
~ 50uA for V
DD
= +2.7V and I
W
~ 400uA for V
DD
=+5V. See test circuit figure xxxx
Resistor termnals W,B have no limtations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
Common mode leakage current is a measure of the DC leakage fromany termnal B and W to a common mode bias level of V
DD
/ 2.
P
DISS
is calculated from(I
DD
x V
DD
) + (I
SS
x V
SS
)
Applies to Photo Diode of Optical Receiver.
All dynamc characteristics use V
DD
= +5V and V
SS
= 0V
See timng diagramfor location of measured values. All input control voltages are specified with t
R
=t
F
=2.5ns(10% to 90% of 3V) and timed froma voltage level of 1.5V. Switching characteristics
are measured using both V
DD
= +3V and +5V.
Propagation delay depends on value of V
DD
, R
PULL_UP
, and C
L
see applications text.
RDY pin low only for commands 2, 3, 8, 9, 10, and
PR
hardware pulse: CMD_8 ~ 1ms; CMD_9,10 ~0.1ms; CMD_2,3 ~20ms. Device operation at T
A
=-40
o
C & VDD<+3V extends the save time
to 35ms.
Parts can be operated at +2.7V single supply, except from0
o
C to –40
o
C where mnimum+3V is needed
The ADN2850 contains 16,000 transistors. Die size: 100 ml x 150 ml, 10,500 sq. ml.
Retention lifetime equivalent at junction temperature (T
J
) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV will derate with junction
temperature as shown in Figure xxx in the Flash/EE Memory description section of this data sheet.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
Specifications Subject to Change without Notice
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