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參數(shù)資料
| 型號： | ADN4600ACPZ-R7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CROSSPOINT SWITCH 8X8 64LFCSP |
| 標準包裝： | 1 |
| 系列： | XStream™ |
| 功能： | 交叉點開關 |
| 電路： | 1 x 8:8 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 1.7 V ~ 3.6 V |
| 電流 - 電源： | 460mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 標準包裝 |
| 其它名稱： | ADN4600ACPZ-R7DKR |
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ADN4600
Data Sheet
Rev. A | Page 16 of 28
TRANSMITTERS
Output Structure and Output Levels
The ADN4600 transmitter outputs incorporate 50 Ω termination
resistors, ESD protection, and output current switch. Each
channel provides independent control of both the absolute
output level and the pre-emphasis output level. It should be
noted that the choice of output level affects the output common-
mode level. A 600 mV p-p differential output level with full
pre-emphasis range requires an output termination voltage
of 2.5 V or greater; therefore, for the VTTO pin, VCC must be
equal to or greater than 2.5 V.
Pre-Emphasis
The total output amplitude and pre-emphasis setting space is
reduced to a single map of basic settings that provides seven
settings of output equalization to ease programming for typical
channels. The full resolution of seven settings is available through
the I2C interface by writing to Bits[2:0] (the TX PE[2:0] bits) of
the TX[7:0] configuration registers. Table 10 summarizes the
absolute output level, pre-emphasis level, and high frequency
boost for each of the control settings and the typical length of
FR4 trace compensated for by each setting.
Full control of the transmit output levels is available through the
I2C control interface. This full control is achieved by writing to
the TX[7:0] Output Level Control[1:0] registers for the channel
of interest. The supported output levels are shown in Table 12.
The TX[7:0] Output Level Control[1:0] registers must be
programmed to one of the supported settings listed in this table;
other settings are not supported.
The output equalization is optimized for less than 2.5 Gbps
operation, but can be optimized for higher speed applications
up to 4.25 Gbps through the I2C control interface by writing to
the TX DATA RATE bit (Bit 4) of the TX[7:0] configuration
register, with high representing 4.25 Gbps and low representing
2.5 Gbps. The TX[7:0] CTL SRC bit (Bit 7) in the TX[7:0]
Output Level Control 1 register determines whether the pre-
emphasis and output current controls for the channel of interest
are selected from the optimized map or directly from the
TX[7:0] Output Level Control[1:0] registers (per channel).
Setting this bit high selects pre-emphasis control directly from
the TX[7:0] Output Level Control[1:0] registers, and setting it
low selects pre-emphasis control from the optimized map.
VCC
VTTO
OPx
ONx
VEE
TX SIMPLIFIED DIAGRAM
Q1
Q2
IT
RN
52
RP
52
ON-CHIP
TERMINATION
V3
VC
V2
VP
V1
VN
IDC + TPE
07061-
006
ESD
Figure 29. Simplified Output Structure
Table 10. Transmit Pre-Emphasis Boost and Overshoot vs. Setting
TX PE
Boost (dB)
Overshoot
DC Swing (mV p-p Differential)
Typical FR4 Trace Length (Inches)
0
0%
800
0 to 5
1
2
25%
800
0 to 5
2
3.5
50%
800
10 to 15
3
4.9
75%
800
15 to 20
4
6
100%
800
25 to 30
5
7.4
133%
600
30 to 35
6
9.5
200%
400
35 to 40
Table 11. Transmitters Control Registers
Name
Addr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Def.
TX[7:0]
Configuration
0xE0, 0xE8,
0xF0, 0xF8,
0xD8, 0xD0,
0xC8, 0xC0
TX EN
TX data
rate
TX PE[2]
TX PE[1]
TX PE[0]
0x20
TX[7:0] Output
Level Control 1
0xE1, 0xE9,
0xF1, 0xF9,
0xD9, 0xD1,
0xC9, 0xC1
TX[7:0]
CTL SRC
TX[7:0]_OLEV1[6:0]
0x40
TX[7:0] Output
Level Control 0
0xE2, 0xEA,
0xF2, 0xFA,
0xDA, 0xD2,
0xCA, 0xC2
TX[7:0]_OLEV0[6:0]
0x40
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