VCC R
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� ADN4662BRZ
寤犲晢锛� Analog Devices Inc
鏂囦欢闋佹暩(sh霉)锛� 8/12闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC RCVR DIFF LVDS 1CH 8SOIC
妯欐簴鍖呰锛� 98
椤炲瀷锛� 绶氳矾鎺ユ敹鍣�
椹�(q奴)鍕曞櫒/鎺ユ敹鍣ㄦ暩(sh霉)锛� 0/1
瑕�(gu墨)绋嬶細 LVDS
闆绘簮闆诲锛� 3 V ~ 3.6 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-SOIC锛�0.154"锛�3.90mm 瀵級
渚涙噳鍟嗚ō鍌欏皝瑁濓細 8-SO
鍖呰锛� 绠′欢
鐢�(ch菐n)鍝佺洰閷勯爜闈細 765 (CN2011-ZH PDF)
Data Sheet
ADN4662
Rev. A | Page 5 of 12
Test Circuits and Timing Diagrams
VCC
ROUT
RIN+
CL
SIGNAL
GENERATOR
50
RIN鈥�
CL = LOAD AND TEST JIG CAPACITANCE
07960-
002
Figure 2. Test Circuit for Receiver Propagation Delay and Transition Time
20%
80%
20%
1.5V
tPLHD
tPHLD
RIN鈥�
RIN+
0V (DIFFERENTIAL)
tTLH
tTHL
VOH
VOL
1.2V
1.3V
1.1V
ROUT
VID = 200mV
07960-
003
Figure 3. Receiver Propagation Delay and Transition Time Waveforms
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鍙冩暩(sh霉)鎻忚堪
ADN4662BRZ 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:Transceiver IC
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ADN4663 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:High Speed Differential Driver
ADN4663BRZ 鍔熻兘鎻忚堪:IC DRIVER DIFF LVDS 2CH 8SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鎺ュ彛 - 椹�(q奴)鍕曞櫒锛屾帴鏀跺櫒锛屾敹鐧�(f膩)鍣� 绯诲垪:- 妯欐簴鍖呰:1 绯诲垪:- 椤炲瀷:绶氳矾鏀剁櫦(f膩)鍣� 椹�(q奴)鍕曞櫒/鎺ユ敹鍣ㄦ暩(sh霉):5/3 瑕�(gu墨)绋�:RS232 闆绘簮闆诲:3 V ~ 5.5 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳鍟嗚ō鍌欏皝瑁�:28-SOIC 鍖呰:Digi-Reel® 鐢�(ch菐n)鍝佺洰閷勯爜闈�:918 (CN2011-ZH PDF) 鍏跺畠鍚嶇ū:296-25096-6
ADN4663BRZ 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:Transceiver IC
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