參數(shù)資料
型號(hào)： ADN4697EBRZ-RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 6/20頁(yè)
文件大?。?/td> 0K
描述： IC TXRX LVDS 2CH 14SOIC
標(biāo)準(zhǔn)包裝： 1,000
系列： *
ADN4696E/ADN4697E
Data Sheet
Rev. 0 | Page 14 of 20
THEORY OF OPERATION
The ADN4696E/ADN4697E are transceivers for transmitting
and receiving multipoint low voltage differential signalling
(M-LVDS) at high speed (data rates up to 200 Mbps). Each
device has a differential line driver and a differential line
receiver, allowing each device to send and receive data.
Multipoint LVDS expands on the established LVDS low voltage
differential signalling method by allowing bidirectional com-
munication between more than two nodes. Up to 32 nodes can
be connected on an M-LVDS bus.
HALF-/FULL-DUPLEX OPERATION
Half-duplex operation allows a transceiver to transmit or
receive, but not both at the same time. However, with full-
duplex operation, a transceiver can transmit and receive
simultaneously. The ADN4696E is a half-duplex device in
which the driver and the receiver share differential bus
terminals. The ADN4697E is a full-duplex device that has
dedicated driver output and receiver input pins. Figure 37 and
Figure 38 show typical half-and full-duplex bus topologies for
M-LVDS.
THREE-STATE BUS CONNECTION
The outputs of the device can be placed in a high impedance
state by disabling the driver or receiver. This allows several
driver outputs to be connected to a single M-LVDS bus. Note
that on each bus line only one driver should be enabled at a
time, but that many receivers can be enabled.
The driver can be enabled or disabled using the driver enable
(DE) pin. This enables the driver outputs when taken high, or
puts the driver outputs into a high impedance state when taken
low. Similarly, an active low receiver enable (RE) pin controls
the receiver. Taking this pin low enables the receiver, whereas
taking it high puts the receiver outputs into a high impedance
state.
Truth tables for driver and receiver output states under various
conditions are shown in Table 8, Table 9, and Table 10.
TRUTH TABLES
Table 7. Truth Table Abbreviations
Letter
Description
H
High level
L
Low level
X
Don’t care
I
Indeterminate
Z
High impedance (off)
NC
Disconnected
Driver, Half Duplex (ADN4696E)
Table 8. Transmitting (See Table 7 for Abbreviations)
Power
Inputs
Outputs
DE
DI
A
B
Yes
H
L
Yes
H
L
H
Yes
H
NC
L
H
Yes
L
X
Z
Yes
NC
X
Z
≤1.5 V
X
Z
Driver, Full Duplex (ADN4697E)
Table 9. Transmitting (See Table 7 for Abbreviations)
Power
Inputs
Outputs
DE
DI
Y
Z
Yes
H
L
Yes
H
L
H
Yes
H
NC
L
H
Yes
L
X
Z
Yes
NC
X
Z
≤1.5 V
X
Z
Type 2 Receiver (ADN4696E/ADN4697E)
Table 10. Receiving (See Table 7 for Abbreviations)
Power
Inputs
Output
A B
RE
RO
Yes
≥150 mV
L
H
Yes
≤50 mV
L
Yes
50 mV < A B < 150 mV
L
I
Yes
NC
L
Yes
X
H
Z
Yes
X
NC
Z
No
X
Z
GLITCH-FREE POWER-UP/DOWN
To minimize disruption to the bus when adding nodes, the
M-LVDS outputs of the device are kept glitch-free when
powering up or down. This allows insertion of devices onto a live
M-LVDS bus, because the bus outputs are not switched on
before the device is fully powered. Additionally, all outputs are
placed in a high impedance state when the device is powered off.
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