參數(shù)資料
型號: ADP1650ACBZ-R7
廠商: ANALOG DEVICES INC
元件分類: 顯示驅(qū)動器
英文描述: LED DISPLAY DRIVER, PBGA12
封裝: 2 X 1.50 MM, ROHS COMPLIANT, WLCSP-12
文件頁數(shù): 28/32頁
文件大?。?/td> 1423K
代理商: ADP1650ACBZ-R7
ADP1650
Rev. C | Page 5 of 32
RECOMMENDED SPECIFICATIONS: INPUT AND OUTPUT CAPACITANCE AND INDUCTANCE
Table 2.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
CAPACITANCE
CMIN
Input
TA = 40°C to +125°C
4.0
10
μF
Output
TA = 40°C to +125°C
3.0
10
20
μF
MINIMUM AND MAXIMUM INDUCTANCE
L
TA = 40°C to +125°C
0.6
1.0
1.5
μH
I2C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS
Table 3.
Parameter1
Min
Max
Unit
Description
fSCL
400
kHz
SCL clock frequency
tHIGH
0.6
μs
SCL high time
tLOW
1.3
μs
SCL low time
tSU, DAT
100
ns
Data setup time
tHD, DAT
0
0.9
μs
Data hold time
tSU, STA
0.6
μs
Setup time for repeated start
tHD, STA
0.6
μs
Hold time for start/repeated start
tBUF
1.3
μs
Bus free time between a stop and a start condition
tSU, STO
0.6
μs
Setup time for stop condition
tR
20 + 0.1 CB2
300
ns
Rise time of SCL and SDA
tF
20 + 0.1 CB2
300
ns
Fall time of SCL and SDA
tSP
0
50
ns
Pulse width of suppressed spike
400
pF
Capacitive load for each bus line
1 Guaranteed by design.
2 CB is the total capacitance of one bus line in picofarads.
SDA
SCL
S
S = START CONDITION
Sr = REPEATED START CONDITION
P = STOP CONDITION
Sr
P
S
tLOW
tR
tHD, DAT
tHIGH
tSU, DAT
tF
tSU, STA
tHD, STA
tSP
tSU, STO
tBUF
tR
08
83
7-
0
03
Figure 3. I2C-Compatible Interface Timing Diagram
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