參數(shù)資料
型號: ADP3152
廠商: Analog Devices, Inc.
英文描述: 5-Bit Programmable Synchronous Switching Regulator Controller(用于PⅡ處理器的5位可編程同步開關(guān)穩(wěn)壓控制器)
中文描述: 5位可編程同步開關(guān)穩(wěn)壓器控制器(用于PⅡ處理器的5位可編程同步開關(guān)穩(wěn)壓控制器)
文件頁數(shù): 2/12頁
文件大?。?/td> 240K
代理商: ADP3152
ADP3152
–10–
REV. 0
CIN Selection and Input Current di/dt Reduction
In continuous-inductor-current mode, the source current of the
high side MOSFET is a square wave with a duty ratio of VO/
VIN. To keep the input ripple voltage at a low value, one or
more capacitors with low equivalent series resistance (ESR) and
adequate ripple-current rating must be connected across the
input terminals. The maximum rms current of the input bypass
capacitors is:
ICINRMS
≈ [V
O(VIN – VO)]
0.5 I
OMAX /VIN = 7 Arms
Let us select the FA-type capacitor with 2700
F capacitance
and 10 V voltage rating. The ESR of that capacitor is 34 m
and the allowed ripple current at 100 kHz is 1.94 A. At 105
°C
we would need to connect at least four such capacitors in paral-
lel to handle the calculated ripple current. At 50
°C ambient,
however, the ripple current can be increased, so three capacitors
in parallel are adequate.
The ripple voltage across the three paralleled capacitors is:
VCINRPL = IOMAX [ESRIN/3 + DMAXHF /(3CIN fMIN )]
140 mV p-p
To further reduce the effect of the ripple voltage on the system
supply voltage bus and to reduce the input-current di/dt to
below the recommended maximum of 0.1 A/
s, an additional
small inductor (L > 1.7
H @ 10 A) should be inserted between
the converter and the supply bus (see Figure 2).
Feedback Loop Compensation Design
To keep the peak-to-peak output voltage deviation as small as
possible, the low frequency output impedance (i.e., the output
resistance) of the converter should be made equal to the ESR of
the output capacitor. That can be achieved by having a single-pole
roll-off of the voltage gain of the gm error amplifier, where the pole
frequency coincides with the ESR zero of the output capacitor. A
gain with single-pole roll-off requires that the gm amplifier is termi-
nated by the parallel combination of a resistor and capacitor. The
required resistor value can be calculated from the equation:
36
× R
SENSE
g
m
145 k
R
COMP
()
= R
E
where gm = 2.2 ms and the quantities 36 and 145 k
are charac-
teristic of the ADP3152. The calculated compensating resis-
tance is:
R1 R2 = RCOMP = 31 k
The compensating capacitance is determined from the equality
of the pole frequency of the error amplifier gain and the zero
frequency of the impedance of the output capacitor.
CCOMP
=
RECOUT
RCOMP
=
5 m
×16.2 mF
31 k
= 2.6 nF
In the application circuit we tested, we found that the compen-
sation scheme shown in Figure 2 gave the optimal response to
meet the Pentium II dc/dc static and transient specifications
with sufficient margins including the ADP3152’s initial error
tolerance, the PCB layout trace resistances, and the external
component parasitics. If we increase the load resistance to the
COMP pin, the static regulation will improve. The load transient
response, however, will get worse. In Figure 2, if we decrease the
R1 = 150 k
resistor vs. the R2 = 39 k resistor, the regulation
band will shift positive in relation to the 2.8 V. If we increase
the R1 resistor, the regulation band will shift negative. It may be
necessary to adjust these resistor values to obtain the best static
and dynamic regulation compliance depending on the output
capacitor ESR and the parasitic trace resistances of the PCB
layout.
BOARD LAYOUT
A multilayer PCB is recommended with a minimum of two
copper layers. One layer on top should be used for traces inter-
connecting low power SMT components. The ground terminals
of those components should be connected with vias to the bot-
tom traces connecting directly to the ADP3152 ground pins.
One layer should be a power ground plane. If four layers are
possible, one additional layer should be an internal system
ground plane, and one additional layer can be used for other
system interconnections.
When laying out the printed circuit board, the following check-
list should be used to ensure proper operation of the ADP3152.
It is advisable to follow the evaluation board layout as closely as
possible. If necessary, contact Analog Devices Application Engi-
neering for layout suggestions.
相關(guān)PDF資料
PDF描述
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