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參數(shù)資料
| 型號(hào)： | ADPLP01 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | GSM Baseband Processing Chipset |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP176 |
| 封裝： | LOW PROFILE, PLASTIC, TQFP-176 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大小： | 62K |
| 代理商： | ADPLP01 |
AD20msp410
–5–
REV. 0
Analog Voice Interface to BBC
T he analog voice interface to the BBC is specified in the
AD7015 data sheet. Several design examples are given for
single-ended or differential inputs or outputs. A voltage
reference for biasing the microphone signal is provided on the
BBC. T he analog output of the BBC is capable of driving an
earpiece directly with and impedance of 150
. For optional
use of a separate external microphone and power amplifier, a set
of auxiliary inputs/outputs is provided.
Radio Interface to BBC and PLP
T he analog interface between the BBC and the radio subsystem
consists of differential inputs and outputs for the I and Q parts
of the signal and three analog control signals for AFC, AGC and
transmit ramp envelope. Details of these signals are specified in
the AD7015 data sheet. T he digital interface between the PLP
and the radio subsystem consists of a serial port for communi-
cating with the synthesizers and several control signals as
specified in detail in the ADPLP01 data sheet.
Digital SIM Card Interface to PLP
T he PLP is designed to interface directly to the SIM. However
interface logic may be necessary to connect the 3 V chipset to a
5 V SIM.
Digital Interface to K eypad
K eypad interface logic for up to 40 keys is provided on the PLP.
T his interface provides keyboard scan for 8 Rows and 4
columns. Additionally an extra pin on the PLP is provided for
the power switch.
Digital Bus Interface to Memory and Display
External RAM and ROM as well as the display controller
interfaces directly to the 21-bit address bus and 16-bit data bus
of the PLP.
Interface to FLASH Memory
T he large FLASH memory can contain all programs for the
embedded Control Processor of the PLP. T his includes the
complete GSM protocol software as well as the User Interface
Software. A size of 4 Mbit to 8 Mbit is suggested to accommo-
date all Protocol software plus a typical size of User Interface
Software. Enhanced features, requiring larger memories are
supported easily by the large address space of the embedded
Control Processor. T o facilitate production programming and
field upgrades of the FLASH memories, the PLP provides
embedded code to download the software into the FLASH
memory via its standard serial port.
Interface to SRAM
Beside the FLASH memory, the Control Processor additionally
supports static RAM to store user defined variables, typically
those used by the Protocol Stack or Application Layer. Standard
SRAMs interface directly to the address and data bus of the
PLP.
Interface to Display Controller
T his interface is achieved through the address and data buses
and associated read and write strobes, as well as a specific
enable signal. An integrated wait state generator helps interface
to a wide range of display controllers. T wo pins with PWM
outputs control the intensity of separate backlights for display
and keypad.
Full engineering and test mode support
Support for all phase 1 and phase 2 handover modes
SIM Interface driver
Message interfacing to Layer 3 (Radio Resources Manager)
and Layer 2 (data link layer, both signaling and data)
External functions for AGC, AFC and synthesizer setting are
called by Layer 1. T hese allow the user to configure the
system for a wide range of radio architectures including the
T T P GSM reference radio.
T he higher layers of the protocol stack also reside on this
embedded processor. A GSM Phase 2 compliant, Layer 2/3
protocol stack is available from T he T echnology Partnership.
POWE R DISSIPAT ION CONSIDE RAT IONS
In mobile applications, minimizing the power consumption of
all devices is critical to achieving longer standby and talk times.
In a GSM handset the baseband subsystem dominates the
current consumption of the phone in standby. T he design of the
ASP, PLP and BBC includes extensive features to reduce current
consumption and give standby times of up to 70 hours.
All three devices were specifically designed to operate from
2.7 V to 3.6 V, so facilitating three or four cell NiCad/NiMH or
single-cell Li Ion batteries.
T he PLP incorporates intelligent power management, permit-
ting automatic control of power consumption in the PLP and
the peripheral circuitry. Data processing modules are switched
on only when they process data, otherwise they are powered
down.
Additional control signals are provided that enable the Layer 1
software to control the external subsystems, such as the ASP,
BBC, radio and memory components, so that their power is
intelligently switched by the PLP.
Within the ASP the different powerdown modes range from a
simple “wait for interrupt” state to a complete hardware
powerdown, with only leakage currents dissipating power.
In the BBC, the powerdown functions are split separately
between receive, transmit and auxiliary circuits. T his provides
optimal analog power performance when operating in different
modes.
INT E RFAC E S
Figure 5 shows the chipset’s eight interfaces, which have to be
considered in the design of the complete mobile radio. Some of
these interfaces have to meet GSM specifications, others will be
design specific.
Analog Voice Interface to BBC
Radio Interface to BBC and PLP
Digital SIM Card Interface to PLP
Digital Interface to the K eypad
Digital Bus Interface from PLP to Memory and Display
Digital Interface from the PLP to the EEPROM
Digital Audio Interface (DAI)
Digital Interface to PLP for Data Services
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