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參數(shù)資料
| 型號： | ADS-238Q |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 12-Bit, 20MHz, Low Power Sampling A/D Converters |
| 中文描述： | 12位，20MHz的，低功耗采樣A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 83K |
| 代理商： | ADS-238Q |
ADS-238Q
5
Figure 8. ADS-238Q Timing Diagram
Figure 7. Clock to Output Delay vrs V
S
Clock
The ADS-238Q accepts a low voltage CMOS logic level at
the clock input (CLK, pin 2). The clock duty cycle must be
held to within 50% +/-3% because consecutive stages of
the A-to-D are clocked in opposite phase. A duty cycle
other than this will reduce the settling time available for
every other stage, there by degrading dynamic
performance.
For optimum performance at high input frequencies the
clock must have low jitter, and rise/fall times less than 2ns.
Over/undershoot should be avoided. Clock jitter causes
the noise floor to increase proportional to the input
frequency. To reduce crosstalk, and hence jitter, clock
traces on the PC board should be kept as short as
possible with transmission line practices employed.
Digital Outputs
The digital output data is provided in offset binary format,
at 3.3V CMOS logic levels, and is available 7.5 clock
cycles after the data is sampled. The output data is invalid
for the first 20 clock cycles when the ADS-238Q is first
powered up.
The clock to output delay is typically 8ns, but will change
as a function of the supply voltage, V
S
. Figure 7, Clock to
Output Delay vrs V
S
, shows this relationship.
A negative full scale input results in an all zeros output
code (0000 0000 0000). A positive full scale input results
in an all ones output code (1111 1111 1111).
The input is sampled during the high-to-low transition of
the input clock. Output data should be latched during the
low-to-high clock transition as shown in Figure 8, Timing
Diagram.
Power Supplies and Grounding
The ADS-238Q is powered from a single 3.3V supply. The
converters should be mounted on a board that provides
separate low impedance paths for the analog and digital
supplies and grounds. For best performance the 3.3V
supply should be clean, and linearly regulated. The power
supply should be bypassed to ground with a 10μF tantalum
capacitor in parallel with a 0.01μF ceramic capacitor.
Locate the bypass capacitors as close to the converter as
possible. Analog and digital grounds should be isolated
with a ferrite bead. See the Typical Connection Diagram,
Figure 2.
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
2.5
V
S
C
3.1
2.8
3.4
3.7
V
IN
t
AP
t
D
CLK
N-1
N-2
N-1
N
N
N+1
N+2
N+6
N+7
N+8
D
OUT
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