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參數(shù)資料
| 型號： | ADS-927MM |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 串行ADC |
| 英文描述： | 14-Bit, 1MHz, Low-Power Sampling A/D Converters |
| 中文描述： | 14位，1MHz的，低功耗采樣A / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 150K |
| 代理商： | ADS-927MM |
ADS -927
3
+25°C
0 to +70°C
–55 to +125°C
ANALOG OUTPUT
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
UNITS
Internal Reference
Voltage
Drift
External Current
+9.95
—
—
+10.0
±5
—
+10.05
—
1.5
+9.95
—
—
+10.0
±5
—
+10.05
—
1.5
+9.95
—
—
+10.0
±5
—
+10.05
—
1.5
Volts
ppm/°C
mA
DIGITAL OUTPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
Delay, Falling Edge of EOC
to Output Data Valid
Output Coding
+2.4
—
—
—
—
—
—
—
—
+0.4
–4
+4
+2.4
—
—
—
—
—
—
—
—
+0.4
–4
+4
+2.4
—
—
—
—
—
—
—
—
+0.4
–4
+4
Volts
Volts
mA
mA
—
—
35
—
—
35
—
—
35
ns
Offset Binary
POWER REQUIREMENTS, ±15V
Power Supply Ranges
+15V Supply
–15V Supply
+5V Supply
Power Supply Currents
+15V Supply
–15V Supply
+5V Supply
Power Dissipation
Power Supply Rejection
+14.5
–14.5
+4.75
+15.0
–15.0
+5.0
+15.5
–15.5
+5.25
+14.5
–14.5
+4.75
+15.0
–15.0
+5.0
+15.5
–15.5
+5.25
+14.5
–14.5
+4.75
+15.0
–15.0
+5.0
+15.5
–15.5
+5.25
Volts
Volts
Volts
—
—
—
—
—
+43
–25
+71
1.6
—
+65
–45
+80
1.95
±0.02
—
—
—
—
—
+43
–25
+71
1.6
—
+65
–45
+80
1.95
±0.02
—
—
—
—
—
+43
–25
+71
1.6
—
+65
–45
+80
1.95
±0.02
mA
mA
mA
Watts
%FSR/%V
POWER REQUIREMENTS, ±12V
Power Supply Ranges
+12V Supply
–12V Supply
+5V Supply
Power Supply Currents
+12V Supply
–12V Supply
+5V Supply
Power Dissipation
Power Supply Rejection
+11.5
–11.5
+4.75
+12.0
–12.0
+5.0
+12.5
–12.5
+5.25
+11.5
–11.5
+4.75
+12.0
–12.0
+5.0
+12.5
–12.5
+5.25
+11.5
–11.5
+4.75
+12.0
–12.0
+5.0
+12.5
–12.5
+5.25
Volts
Volts
Volts
—
—
—
—
—
+42
–25
+71
1.4
—
+65
–45
+80
1.65
±0.02
—
—
—
—
—
+42
–25
+71
1.4
—
+65
–45
+80
1.65
±0.02
—
—
—
—
—
+42
–25
+71
1.4
—
+65
–45
+80
1.65
±0.02
mA
mA
mA
Watts
%FSR/%V
6.02
(SNR + Distortion) – 1.76 + 20 log
Full Scale Amplitude
Actual Input Amplitude
Effective bits is equal to:
This is the time required before the A/D output data is valid after the analog input
is back within the specified range.
Footnotes:
All power supplies must be on before applying a start convert pulse. All supplies
and the clock (START CONVERT) must be present during warmup periods. The
device must be continuously converting during this time. There is a slight
degradation in performance when using ±12V supplies.
See Ordering Information for 0 to +10V input range. Contact DATEL for
availability of other input voltage ranges.
A 1MHz clock with a 200ns wide start convert pulse is used for all production
testing. For applications requiring less than a 1MHz sampling rate, wider start
convert pulses can be used. See Timng Diagramfor more details.
TECHNICAL NOTES
1. Obtaining fully specified performance from the ADS-927
requires careful attention to pc-card layout and power
supply decoupling. The device’s analog and digital ground
systems are connected to each other internally. For optimal
performance, tie all ground pins (14, 19 and 23) directly to
a large
analog
ground plane below the package.
Bypass all power supplies and the REFERENCE OUTPUT
(pin 21) to ground with 4.7μF tantalum capacitors in parallel
with 0.1μF ceramic capacitors. Locate the bypass capaci-
tors as close to the unit as possible. If the user-installed
offset and gain adjusting circuit in Figure 2 is used, also
locate it as close to the ADS-927 as possible.
2. The ADS-927 achieves its specified accuracies without the
need for external calibration. If required, the device's small
initial offset and gain errors can be reduced to zero using
the input circuit of Figure 2. When using this circuit, or any
similar offset and gain-calibration hardware, make adjust-
ments following warmup. To avoid interaction, always
adjust offset before gain.
3. When operating the ADS-927 from ±12V supplies, do not
drive external circuitry with the REFERENCE OUTPUT. The
reference's accuracy and drift specifications may not be
met, and loading the circuit may cause accuracy errors
within the converter.
4. Applying a start convert pulse while a conversion is in
progress (EOC = logic "1") initiates a new and inaccurate
conversion cycle. Data for the interrupted and subsequent
conversions will be invalid.
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