參數(shù)資料
型號: ADS1232IPWG4
廠商: Texas Instruments
文件頁數(shù): 10/39頁
文件大小: 0K
描述: IC ADC 24-BIT 10/80SPS 24-TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Basics
視頻文件: Nuts and Bolts of the Delta-Sigma Converter
標(biāo)準(zhǔn)包裝: 60
位數(shù): 24
采樣率(每秒): 10,80
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 13.1mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
輸入數(shù)目和類型: 4 個單端,單極;2 個差分,雙極
配用: 296-20803-ND - EVALUATION MODULE FOR ADS1232
www.ti.com
DATA RATE
DATA READY/DATA OUTPUT (DRDY/DOUT)
SERIAL CLOCK INPUT (SCLK)
DATA FORMAT
SBAS350F – JUNE 2005 – REVISED FEBRUARY 2008
The ADS1232/4 data rate is set by the SPEED pin,
This digital output pin serves two purposes. First, it
as shown in Table 7. When SPEED is low, the data
indicates when new data are ready by going low.
rate is nominally 10SPS. This data rate provides the
Afterwards, on the first rising edge of SCLK, the
lowest noise, and also has excellent rejection of both
DRDY/DOUT
pin
changes
function
and
begins
50Hz
and
60Hz
line-cycle
interference.
For
outputting the conversion data, most significant bit
applications requiring fast data rates, setting SPEED
(MSB) first. Data are shifted out on each subsequent
high selects a data rate of nominally 80SPS.
SCLK rising edge. After all 24 bits have been
retrieved, the pin can be forced high with an
Table 7. Data Rate Settings
additional SCLK. It will then stay high until new data
are ready. This configuration is useful when polling
DATA RATE
on the status of DRDY/DOUT to determine when to
SPEED
Internal Oscillator
External
begin data retrieval.
PIN
or 4.9152MHz Crystal
Oscillator
0
10SPS
fCLKIN / 491,520
1
80SPS
fCLKIN / 61,440
This digital input shifts serial data out with each rising
edge. This input has built-in hysteresis, but care
should still be taken to ensure a clean signal. Glitches
or slow-rising signals can cause unwanted additional
The ADS1232/4 output 24 bits of data in binary two’s
shifting. For this reason, it is best to make sure the
complement format. The least significant bit (LSB)
rise-and-fall times of SCLK are less than 50ns.
has a weight of 0.5VREF/(2
23
– 1). The positive
full-scale input produces an output code of 7FFFFFh
and the negative full-scale input produces an output
code of 800000h. The output clips at these codes for
signals exceeding full-scale. Table 8 summarizes the
ideal output codes for different input signals.
Table 8. Ideal Output Code vs Input Signal(1)
INPUT SIGNAL VIN
(AINP – AINN)
IDEAL OUTPUT CODE
≥ +0.5VREF/Gain
7FFFFFh
(+0.5VREF/Gain)/(2
23 – 1)
000001h
0
000000h
(–0.5VREF/Gain)/(2
23 – 1)
FFFFFFh
≤ –0.5VREF/Gain
800000h
(1)
Excludes effects of noise, INL, offset, and gain errors.
18
Copyright 2005–2008, Texas Instruments Incorporated
Product Folder Link(s): ADS1232 ADS1234
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